Inventor

Michael A. Guillorn

Inventor

Yorktown Heights, NY, US

Overview

2003–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 230 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices23%

H01LSemiconductor devices20%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%

B82YSpecific uses or applications of nanostructures8%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices4%

G06FElectric digital data processing3%

H10BElectronic memory devices2%

B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems2%

PatentTitleYear

11,075,265Trigate device with full silicided epi-less source/drain for high density access transistor applications2021 11,069,775Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETS2021 11,004,678Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer2021 11,004,933Field effect transistor structures2021 10,990,747Automatic generation of via patterns with coordinate-based recurrent neural network (RNN)2021 10,949,601Reducing chemoepitaxy directed self-assembled defects2021 10,921,715Semiconductor structure for optical validation2021 10,840,381Nanosheet and nanowire MOSFET with sharp source/drain junction2020 10,804,278High density programmable e-fuse co-integrated with vertical FETs2020 10,741,641Dielectric isolation and SiGe channel formation for integration in CMOS nanosheet channel devices2020 10,706,200Generative adversarial networks for generating physical design layout patterns of integrated multi-layers2020 10,699,055Generative adversarial networks for generating physical design layout patterns2020 10,699,955Techniques for creating a local interconnect using a SOI wafer2020 10,680,061Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETs2020 10,658,461Nanowire with sacrificial top wire2020 10,650,111Electrical mask validation2020 10,621,302Classification and localization of hotspots in integrated physical design layouts2020 10,621,301Coordinates-based variational autoencoder for generating synthetic via layout patterns2020 10,615,281Semiconductor device including wrap around contact and method of forming the semiconductor device2020 10,606,975Coordinates-based generative adversarial networks for generating synthetic physical design layout patterns2020 10,606,980Method and recording medium of reducing chemoepitaxy directed self-assembled defects2020 10,600,680Chemoepitaxy etch trim using a self aligned hard mask for metal line to via2020 10,599,807Automatic generation of via patterns with coordinate-based recurrent neural network (RNN)2020 10,592,635Generating synthetic layout patterns by feedforward neural network based variational autoencoders2020 10,586,854Gate-all-around field effect transistor having multiple threshold voltages2020 10,580,858Preventing threshold voltage variability in stacked nanosheets2020 10,573,714Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETs2020 10,559,670Nanosheet field effect transistors with partial inside spacers2020 10,522,342Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer2019 10,497,779Stacked nanowire semiconductor device2019 10,438,956High density programmable e-fuse co-integrated with vertical FETs2019 10,429,743Optical mask validation2019 10,411,120Self-aligned inner-spacer replacement process using implantation2019 10,395,922Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer2019 10,367,062Co-integration of silicon and silicon-germanium channels for nanosheet devices2019 10,340,340Multiple-threshold nanosheet transistors2019 10,325,983Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETs2019 10,312,321Trigate device with full silicided epi-less source/drain for high density access transistor applications2019 10,297,512Method of making thin SRAM cell having vertical transistors2019 10,276,695Self-aligned inner-spacer replacement process using implantation2019 10,256,139Chemoepitaxy etch trim using a self aligned hard mask for metal line to via2019 10,249,739Nanosheet MOSFET with partial release and source/drain epitaxy2019 10,242,920Integrating and isolating NFET and PFET nanosheet transistors on a substrate2019 10,229,917Thin SRAM cell having vertical transistors2019 10,217,817Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETs2019 10,177,226Preventing threshold voltage variability in stacked nanosheets2019 10,170,636Gate-to-bulk substrate isolation in gate-all-around devices2019 10,170,609Internal spacer formation from selective oxidation for Fin-first wire-last replacement gate-all-around nanowire FET2019 10,170,485Three-dimensional stacked junctionless channels for dense SRAM2019 10,170,608Internal spacer formation from selective oxidation for fin-first wire-last replacement gate-all-around nanowire FET2019 10,170,584Nanosheet field effect transistors with partial inside spacers2019 10,170,679Josephson junction with spacer2019 10,170,634Wire-last gate-all-around nanowire FET2019 10,170,552Co-integration of silicon and silicon-germanium channels for nanosheet devices2019 10,153,340Stacked nanowire semiconductor device2018 10,134,905Semiconductor device including wrap around contact, and method of forming the semiconductor device2018 10,128,347Gate-all-around field effect transistor having multiple threshold voltages2018 10,121,855Stacked nanowire semiconductor device2018 10,114,921Method and recording medium of reducing chemoepitaxy directed self-assembled defects2018 10,096,673Nanowire with sacrificial top wire2018 10,096,607Three-dimensional stacked junctionless channels for dense SRAM2018 10,081,740Directed self-assembly2018 10,074,575Integrating and isolating nFET and pFET nanosheet transistors on a substrate2018 10,068,850Trench silicide with self-aligned contact vias2018 10,059,820Hybrid topographical and chemical pre-patterns for directed self-assembly of block copolymers2018 10,056,293Techniques for creating a local interconnect using a SOI wafer2018 10,037,398Pattern decomposition method for wiring patterns with chemoepitaxy based directed self assembly2018 10,037,885Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer2018 10,026,810Co-integration of silicon and silicon-germanium channels for nanosheet devices2018 10,014,214Electronic device including moat power metallization in trench2018 9,997,613Integrated etch stop for capped gate and method for manufacturing the same2018 9,997,519Dual channel structures with multiple threshold voltages2018 9,954,063Stacked planar double-gate lamellar field-effect transistor2018 9,954,062Stacked planar double-gate lamellar field-effect transistor2018 9,941,129Semiconductor device having self-aligned gate contacts2018 9,929,334'Josephson junction with spacer'2018 9,911,592'Method for making nanosheet CMOS device integrating atomic layer deposition process and replacement gate structure'2018 9,911,603'Pattern decomposition for directed self assembly patterns templated by sidewall image transfer'2018 9,884,978'Directed self-assembly'2018 9,871,140'Dual strained nanosheet CMOS and methods for fabricating'2018 9,859,375'Stacked planar double-gate lamellar field-effect transistor'2018 9,853,132Nanosheet MOSFET with full-height air-gap spacer2017 9,852,260Method and recording medium of reducing chemoepitaxy directed self-assembled defects2017 9,831,324Self-aligned inner-spacer replacement process using implantation2017 9,812,321'Method for making nanosheet CMOS device integrating atomic layer deposition process and replacement gate structure'2017 9,786,597'Self-aligned pitch split for unidirectional metal wiring'2017 9,755,017'Co-integration of silicon and silicon-germanium channels for nanosheet devices'2017 9,754,965'Techniques for dual dielectric thickness for a nanowire CMOS technology using oxygen growth'2017 9,748,404'Method for fabricating a semiconductor device including gate-to-bulk substrate isolation'2017 9,738,765'Hybrid topographical and chemical pre-patterns for directed self-assembly of block copolymers'2017 9,728,542'High density programmable e-fuse co-integrated with vertical FETs'2017 9,721,888'Trench silicide with self-aligned contact vias'2017 9,716,036'Electronic device including moat power metallization in trench'2017 9,691,615'Chemoepitaxy-based directed self assembly process with tone inversion for unidirectional wiring'2017 9,685,530'Replacement metal gate dielectric cap'2017 9,684,753'Techniques for generating nanowire pad data from pre-existing design data'2017 9,659,824'Graphoepitaxy directed self-assembly process for semiconductor fin formation'2017 9,653,547'Integrated etch stop for capped gate and method for manufacturing the same'2017 9,647,139'Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer'2017 9,646,883'Chemoepitaxy etch trim using a self aligned hard mask for metal line to via'2017 9,620,622'Replacement metal gate dielectric cap'2017 9,581,899'2-dimensional patterning employing tone inverted graphoepitaxy'2017 9,582,631'Method and system for template pattern optimization for DSA patterning using graphoepitaxy'2017 9,576,817'Pattern decomposition for directed self assembly patterns templated by sidewall image transfer'2017 9,570,550'Stacked nanowire semiconductor device'2017 9,564,502'Techniques for multiple gate workfunctions for a nanowire CMOS technology'2017 9,558,310'Method and system for template pattern optimization for DSA patterning using graphoepitaxy'2017 9,559,284'Silicided nanowires for nanobridge weak links'2017 9,536,794'Techniques for dual dielectric thickness for a nanowire CMOS technology using oxygen growth'2017 9,514,263'Chemo epitaxy mask generation'2016 9,508,829'Nanosheet MOSFET with full-height air-gap spacer'2016 9,496,338'Wire-last gate-all-around nanowire FET'2016 9,484,205'Semiconductor device having self-aligned gate contacts'2016 9,472,499'Self-aligned pitch split for unidirectional metal wiring'2016 9,466,534'Cointegration of directed self assembly and sidewall image transfer patterning for sublithographic patterning with improved design flexibility'2016 9,449,820'Epitaxial growth techniques for reducing nanowire dimension and pitch'2016 9,443,951'Embedded planar source/drain stressors for a finFET including a plurality of fins'2016 9,443,949'Techniques for multiple gate workfunctions for a nanowire CMOS technology'2016 9,437,443'Low-temperature sidewall image transfer process using ALD metals, metal oxides and metal nitrides'2016 9,419,097'Replacement metal gate dielectric cap'2016 9,391,163'Stacked planar double-gate lamellar field-effect transistor'2016 9,385,026'Sublithographic Kelvin structure patterned with DSA'2016 9,385,027'Sublithographic Kelvin structure patterned with DSA'2016 9,368,502'Replacement gate multigate transistor for embedded DRAM'2016 9,362,354'Tuning gate lengths in semiconductor device structures'2016 9,362,355'Nanosheet MOSFET with full-height air-gap spacer'2016 9,349,640'Electrode pair fabrication using directed self assembly of diblock copolymers'2016 9,337,264'Process for forming a surrounding gate for a nanowire using a sacrificial patternable dielectric'2016 9,306,164'Electrode pair fabrication using directed self assembly of diblock copolymers'2016 9,263,550'Gate to diffusion local interconnect scheme using selective replacement gate flow'2016 9,214,529'Fin Fet device with independent control gate'2015 9,209,086'Low temperature salicide for replacement gate nanowires'2015 9,182,369'Manufacturable sub-3 nanometer palladium gap devices for fixed electrode tunneling recognition'2015 9,171,796'Sidewall image transfer for heavy metal patterning in integrated circuits'2015 9,162,877'Lateral etch stop for NEMS release etch for high density NEMS/CMOS monolithic integration'2015 9,128,078'Manufacturable sub-3 nanometer palladium gap devices for fixed electrode tunneling recognition'2015 9,093,379'Silicidation blocking process using optically sensitive HSQ resist and organic planarizing layer'2015 9,087,916'Method for keyhole repair in replacement metal gate integration through the use of a printable dielectric'2015 9,059,096'Method to form silicide contact in trenches'2015 9,053,982'Local tailoring of fingers in multi-finger fin field effect transistors'2015 9,048,258'Narrow body field-effect transistor structures with free-standing extension regions'2015 9,034,704'6T SRAM architecture for gate-all-around nanowire devices'2015 9,029,834'Process for forming a surrounding gate for a nanowire using a sacrificial patternable dielectric'2015 9,024,355'Embedded planar source/drain stressors for a finFET including a plurality of fins'2015 9,018,090'Borderless self-aligned metal contact patterning using printable dielectric materials'2015 9,018,084'Tapered fin field effect transistor'2015 9,013,010'Nanopore sensor device'2015 9,000,530'6T SRAM architecture for gate-all-around nanowire devices'2015 9,000,494'Micromechanical device and methods to fabricate same using hard mask resistant to structure release etch'2015 9,000,556'Lateral etch stop for NEMS release etch for high density NEMS/CMOS monolithic integration'2015 8,993,327'Parallel macromolecular delivery and biochemical/electrochemical interface to cells employing nanostructures'2015 8,993,907'Silicide micromechanical device and methods to fabricate same'2015 8,981,478'Recessed source and drain regions for FinFETs'2015 8,969,965'Fin-last replacement metal gate FinFET'2015 8,946,782'Method for keyhole repair in replacement metal gate integration through the use of a printable dielectric'2015 8,927,312'Method of fabricating MEMS transistors on far back end of line'2015 8,927,405'Accurate control of distance between suspended semiconductor nanowires and substrate surface'2015 8,927,968'Accurate control of distance between suspended semiconductor nanowires and substrate surface'2015 8,921,030'Tone inversion of self-assembled self-aligned structures'2014 8,916,054'High fidelity patterning employing a fluorohydrocarbon-containing polymer'2014 8,900,975'Nanopore sensor device'2014 8,890,261'Fin field effect transistor devices with self-aligned source and drain regions'2014 8,884,370'Narrow body field-effect transistor structures with free-standing extension regions'2014 8,872,241'Multi-direction wiring for replacement gate lines'2014 8,865,531'Multi-direction wiring for replacement gate lines'2014 8,853,790'Semiconductor nanowire structure reusing suspension pads'2014 8,841,652'Self aligned carbide source/drain FET'2014 8,836,087'Gap-fill keyhole repair using printable dielectric material'2014 8,836,048'Field effect transistor device having a hybrid metal gate stack'2014 8,816,328'Patterning contacts in carbon nanotube devices'2014 8,803,129'Patterning contacts in carbon nanotube devices'2014 8,779,414'Collapsable gate for deposited nanostructures'2014 8,771,929'Tone inversion of self-assembled self-aligned structures'2014 8,765,613'High selectivity nitride etch process'2014 8,754,530'Self-aligned borderless contacts for high density electronic and memory device integration'2014 8,741,722'Formation of dividers between gate ends of field effect transistor devices'2014 8,716,695'Compressive (PFET) and tensile (NFET) channel strain in nanowire FETs fabricated with a replacement gate process'2014 8,703,576'Gap-fill keyhole repair using printable dielectric material'2014 8,692,229'Replacement contacts for all-around contacts'2014 8,658,050'Method to transfer lithographic patterns into inorganic substrates'2014 8,658,461'Self aligned carbide source/drain FET'2014 8,656,322'Fin design level mask decomposition for directed self assembly'2014 8,642,403'Replacement contacts for all-around contacts'2014 8,637,371'Non-planar MOSFET structures with asymmetric recessed source drains and methods for making the same'2014 8,637,359'Fin-last replacement metal gate FinFET process'2014 8,610,181'V-groove source/drain MOSFET and process for fabricating same'2013 8,603,868'V-groove source/drain MOSFET and process for fabricating same'2013 8,605,499'Resonance nanoelectromechanical systems'2013 8,592,280'Fin field effect transistor devices with self-aligned source and drain regions'2013 8,586,455'Preventing shorting of adjacent devices'2013 8,586,449'Raised isolation structure self-aligned to fin structures'2013 8,557,648'Recessed source and drain regions for FinFETs'2013 8,536,018'Maskless inter-well deep trench isolation structure and methods of manufacture'2013 8,530,932'Replacement spacer for tunnel FETS'2013 8,513,127'Chemical mechanical planarization processes for fabrication of FinFET devices'2013 8,492,748'Collapsable gate for deposited nanostructures'2013 8,492,208'Compressive (PFET) and tensile (NFET) channel strain in nanowire FETs fabricated with a replacement gate process'2013 8,470,628'Methods to fabricate silicide micromechanical device'2013 8,472,239'Nanowire mesh FET with multiple threshold voltages'2013 8,466,451'Single gate inverter nanowire mesh'2013 8,440,523'Micromechanical device and methods to fabricate same using hard mask resistant to structure release etch'2013 8,432,723'Nano-electro-mechanical DRAM cell'2013 8,422,273'Nanowire mesh FET with multiple threshold voltages'2013 8,415,677'Field-effect transistor device having a metal gate stack with an oxygen barrier layer'2013 8,395,220'Nanomesh SRAM cell'2013 8,334,090'Mixed lithography with dual resist and a single pattern transfer'2012 8,288,236'Field effect transistor having nanostructure channel'2012 8,216,902'Nanomesh SRAM cell'2012 8,178,400'Replacement spacer for tunnel FETs'2012 8,142,877'Nano transfer and nanoreplication using deterministically grown sacrificial nanotemplates'2012 8,084,308'Single gate inverter nanowire mesh'2011 8,003,220'Nanotransfer and nanoreplication using deterministically grown sacrificial nanotemplates'2011 7,947,976'Controlled alignment of catalytically grown nanostructures in a large-scale synthesis process'2011 7,943,196'Nanotransfer and nanoreplication using deterministically grown sacrificial nanotemplates'2011 7,923,337'Fin field effect transistor devices with self-aligned source and drain regions'2011 7,914,970'Mixed lithography with dual resist and a single pattern transfer'2011 7,893,492'Nanowire mesh device and method of fabricating same'2011 7,892,945'Nanowire mesh device and method of fabricating same'2011 7,641,863'Nanoengineered membranes for controlled transport'2010 7,491,934'SEM technique for imaging and measuring electronic transport in nanocomposites based on electric field induced contrast'2009 7,408,186'Controlled alignment catalytically grown nanostructures'2008 7,245,068'Apparatus for controlled alignment of catalytically grown nanostructures'2007 7,229,692'Nanoconduits and nanoreplicants'2007 7,151,256'Vertically aligned nanostructure scanning probe microscope tips'2006 7,144,287'Individually electrically addressable carbon nanofibers on insulating substrates'2006 7,109,515'Carbon containing tips with cylindrically symmetrical carbon containing expanded bases'2006 6,982,519'Individually electrically addressable vertically aligned carbon nanofibers on insulating substrates'2006 6,958,572'Controlled non-normal alignment of catalytically grown nanostructures in a large-scale synthesis process'2005 6,692,324'Single self-aligned carbon containing tips'2004 6,649,431'Carbon tips with expanded bases grown with simultaneous application of carbon source and etchant gases'2003

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2003–2015Patents assigned to UT BATTELLE LLC (17)· patent assignee history

2003–2015Based in Knoxville, TN, US· patent location history

2007–2012Based in Ithaca, NY, US· patent location history

2011–2021Patents assigned to IBM (198)· patent assignee history

2011–2016Patents assigned to GUILLORN MICHAEL A (55)· patent assignee history

2011–2015Patents assigned to CHANG PAUL (13)· patent assignee history

2011–2020Based in Yorktown Heights, NY, US· patent location history

2012–2016Patents assigned to CHANG JOSEPHINE B (31)· patent assignee history

2016–2021Based in Cold Springs, NY, US· patent location history

2016–2020Based in Cold Spring, NY, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	198	2011–2021
GUILLORN MICHAEL Aself	55	2011–2016
CHANG JOSEPHINE B	31	2012–2016
UT BATTELLE LLC	17	2003–2015
CHANG PAUL	13	2011–2015

Locations

Location	Patents	Span
Yorktown Heights, New York, US	127	2011–2020
Cold Springs, New York, US	77	2016–2021
Knoxville, TN, US	12	2003–2015
Cold Spring, New York, US	7	2016–2020
Ithaca, New York, US	4	2007–2012