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Inventor

Yoshifumi Takata

Inventor
Tokyo, JP

Overview

16→
Patents
1990–2014
Patent span
Electricity
Primary field (CPC H)

Patents· 16 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1047%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%
H10DInorganic electric semiconductor devices13%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests13%
H10BElectronic memory devices9%
PatentTitleYear
8,716,122'Method of manufacturing semiconductor device having surface protective films on bond pad'20148,390,134'Semiconductor device having surface protective films on bond pad'20136,890,857'Semiconductor device having a multilayer wiring structure and pad electrodes protected from corrosion, and method for fabricating the same'20056,777,738'Semiconductor integrated circuit'20046,727,170'Semiconductor device having an improved interlayer conductor connections and a manufacturing method thereof'20046,500,675'Manufacturing method of semiconductor device having capacitive element'20026,476,491'Semiconductor device having a multilayer wiring structure and pad electrodes protected from corrosion and method for fabricating the same'20026,448,658'Semiconductor device having improved interconnection-wiring structures'20026,319,812'Method of manufacturing a semiconductor device'20016,278,187'Semiconductor device having an improved interlayer conductor connections and a manufacturing method thereof'20015,712,140'Method of manufacturing interconnection structure of a semiconductor device'19985,561,084'Method of making an interconnection structure of a semiconductor device'19965,475,267'Multilayer interconnection structure for a semiconductor device'19955,442,238'Interconnection structure of a semiconductor device'19955,313,100'Multilayer interconnection structure for a semiconductor device'19944,962,061'Method for manufacturing a multilayer wiring structure employing metal fillets at step portions'1990

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1990–2002Patents assigned to MITSUBISHI ELECTRIC CORP (11)· patent assignee history
1990–2002Based in Hyogo, JP· patent location history
2001–2014Based in Tokyo, JP· patent location history
2002Patents assigned to RYODEN SEMICONDUCTOR SYST ENG (1)· patent assignee history
2004–2005Patents assigned to RENESAS TECH CORP (3)· patent assignee history
2013–2014Patents assigned to RENESAS ELECTRONICS CORP (2)· patent assignee history
2013Patents assigned to HOMMA TAKURO (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MITSUBISHI ELECTRIC CORP111990–2002
RENESAS TECH CORP32004–2005
RENESAS ELECTRONICS CORP22013–2014
HOMMA TAKURO12013
RYODEN SEMICONDUCTOR SYST ENG12002
Locations
LocationPatentsSpan
Tokyo, JP82001–2014
Hyogo, JP81990–2002