Inventor

Takayuki Matsukawa

Inventor
Hyogo, JP

Overview

20→
Patents
1987–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 20 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Bprimary
H10BElectronic memory devices19%
H10DInorganic electric semiconductor devices12%
G06KGraphical data reading10%
G06TImage data processing or generation, in general10%
G06VImage or video recognition or understanding10%
H04NPictorial communication, e.g. television10%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
G08BSignalling systems, e.g. personal calling systems7%
A45DHairdressing or shaving equipment2%
A61BDiagnosis2%
PatentTitleYear
11,087,440Collation device and collation method202110,321,747Makeup assistance device, makeup assistance system, makeup assistance method, and makeup assistance program20199,621,779'Face recognition device and method that update feature amounts at different frequencies based on estimated distance'20179,560,321'Image capturing system, camera control device for use therein, image capturing method, camera control method, and computer program'20179,064,171'Detection device and method for transition area in space'20159,025,875'People counting device, people counting method and people counting program'20157,609,941'Multimedia data recording apparatus, monitor system, and multimedia data recording method'20097,236,690'Event management system'20076,028,346'Isolated trench semiconductor device'20005,300,444'Method of manufacturing a semiconductor device having a stacked structure formed of polycrystalline silicon film and silicon oxide film'19945,274,586'Semiconductor device having a capacitor dielectric film of multilayer structure and a method of controlling the same'19935,182,227'Semiconductor device and method for manufacturing the same'19935,153,689'Semiconductor memory device having bit lines formed of an interconnecting layer of lower reflectance material than the material of the word lines'19925,032,882'Semiconductor device having trench type structure'19914,984,055'Semiconductor device having a plurality of conductive layers and manufacturing method therefor'19914,859,615'Semiconductor memory cell capacitor and method for making the same'19894,847,673'Semiconductor device'19894,835,591'Wiring arrangement for semiconductor devices'19894,794,305'Substrate support structure for ion implantation device'19884,700,457'Method of making multilayer capacitor memory device'1987

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1987–2000Patents assigned to MITSUBISHI ELECTRIC CORP (12)· patent assignee history
1987–1989Based in Itami, JP· patent location history
1988–2000Based in Hyogo, JP· patent location history
2009Based in Tokyo, JP· patent location history
2015–2021Patents assigned to PANASONIC IP MAN CO LTD (6)· patent assignee history
2015–2017Patents assigned to MATSUKAWA TAKAYUKI (4)· patent assignee history
2015–2017Patents assigned to FUJII HIROFUMI (2)· patent assignee history
2015–2017Patents assigned to FUJIMATSU TAKESHI (2)· patent assignee history
2015–2019Based in Kanagawa, JP· patent location history
2021Based in Yokohama-shi, Kanagawa, JP· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MITSUBISHI ELECTRIC CORP121987–2000
PANASONIC IP MAN CO LTD62015–2021
MATSUKAWA TAKAYUKIself42015–2017
FUJII HIROFUMI22015–2017
FUJIMATSU TAKESHI22015–2017
Locations
LocationPatentsSpan
Hyogo, JP91988–2000
Kanagawa, JP52015–2019
Itami, JP31987–1989
Yokohama-shi, Kanagawa, JP12021
Tokyo, JP12009