Inventor
Samit Sengupta
Inventor
San Jose, CA, US
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1021%
H10DInorganic electric semiconductor devices19%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices9%
H01LSemiconductor devices9%
G06FElectric digital data processing7%
G11CStatic stores5%
B24BMachines, devices, or processes for grinding or polishing2%
C23CCoating metallic material2%
G01RMeasuring electric variables2%
PatentTitleYear
10,853,542Fuse-based logic repair202010,490,558Reducing or avoiding mechanical stress in static random access memory (SRAM) strap cells20199,461,040'System and method of varying gate lengths of multiple cores'20169,245,971'Semiconductor device having high mobility channel'20169,076,775'System and method of varying gate lengths of multiple cores'20158,217,457'Electrostatic discharge (ESD) protection device for use with multiple I/O standards'20127,468,617'Electrostatic discharge (ESD) protection device for use with multiple I/O standards'20087,286,020'Techniques for monitoring and replacing circuits to maintain high performance'20076,933,869'Integrated circuits with temperature-change and threshold-voltage drift compensation'20056,459,153'Compositions for improving interconnect metallization performance in integrated circuits'20026,433,433'Semiconductor device with misaligned via hole'20026,413,152'Apparatus for performing chemical-mechanical planarization with improved process window, process flexibility and cost'20026,410,421'Semiconductor device with anti-reflective structure and methods of manufacture'20026,255,226'Optimized metal etch process to enable the use of aluminum plugs'20016,235,609'Method for forming isolation areas with improved isolation oxide'20016,228,757'Process for forming metal interconnects with reduced or eliminated metal recess in vias'20016,207,565'Integrated process for ashing resist and treating silicon after masked spacer etch'20016,176,983'Methods of forming a semiconductor device'20016,162,586'Method for substantially preventing footings in chemically amplified deep ultra violet photoresist layers'20006,146,996'Semiconductor device with conductive via and method of making same'20006,057,587'Semiconductor device with anti-reflective structure'20005,915,203'Method for producing deep submicron interconnect vias'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2001Patents assigned to VLSI TECHNOLOGY INC (4)· patent assignee history
1999–2012Based in San Jose, CA, US· patent location history
2000–2002Patents assigned to PHILIPS ELECTRONICS NA (4)· patent assignee history
2002Patents assigned to KONINKL PHILIPS ELECTRONICS NV (3)· patent assignee history
2005–2012Patents assigned to ALTERA CORP (4)· patent assignee history
2015–2020Patents assigned to QUALCOMM INC (5)· patent assignee history
2015–2020Based in San Diego, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| QUALCOMM INC | 5 | 2015–2020 |
| ALTERA CORP | 4 | 2005–2012 |
| PHILIPS ELECTRONICS NA | 4 | 2000–2002 |
| VLSI TECHNOLOGY INC | 4 | 1999–2001 |
| KONINKL PHILIPS ELECTRONICS NV | 3 | 2002 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 17 | 1999–2012 |
| San Diego, California, US | 5 | 2015–2020 |