Inventor

Douglas M. Reber

Inventor

Austin, TX, US

Overview

1996–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 59 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1031%

H01LSemiconductor devices23%

G06FElectric digital data processing13%

H10DInorganic electric semiconductor devices10%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h109%

B82YSpecific uses or applications of nanostructures2%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%

C23CCoating metallic material1%

G01KMeasuring temperature1%

G01RMeasuring electric variables1%

PatentTitleYear

10,553,508Semiconductor manufacturing using disposable test circuitry within scribe lanes2020 10,522,615Semiconductor package with embedded capacitor and methods of manufacturing same2019 10,510,616Post contact air gap formation2019 10,262,893Method of forming inter-level dielectric structures on semiconductor devices2019 10,204,860Semiconductor device with graphene encapsulated metal and method therefor2019 10,103,241Multigate transistor2018 10,038,081Substrate contacts for a transistor2018 10,014,257Apparatus and method for placing stressors within an integrated circuit device to manage electromigration failures2018 10,008,447Solar cell powered integrated circuit device and method therefor2018 9,934,349Method for verifying design rule checks2018 9,818,642'Method of forming inter-level dielectric structures on semiconductor devices'2017 9,685,405'Fuse/resistor utilizing interconnect and vias and method of making'2017 9,652,577'Integrated circuit design using pre-marked circuit element object library'2017 9,640,430'Semiconductor device with graphene encapsulated metal and method therefor'2017 9,601,354'Semiconductor manufacturing for forming bond pads and seal rings'2017 9,548,266'Semiconductor package with embedded capacitor and methods of manufacturing same'2017 9,515,006'3D device packaging using through-substrate posts'2016 9,508,702'3D device packaging using through-substrate posts'2016 9,508,701'3D device packaging using through-substrate pillars'2016 9,466,569'Though-substrate vias (TSVs) and method therefor'2016 9,455,220'Apparatus and method for placing stressors on interconnects within an integrated circuit device to manage electromigration failures'2016 9,445,050'Teleconferencing environment having auditory and visual cues'2016 9,443,804'Capping layer interface interruption for stress migration mitigation'2016 9,318,409'Integrated circuit heater for reducing stress in the integrated circuit material and chip leads of the integrated circuit, and for optimizing performance of devices of the integrated circuit'2016 9,245,817'Semiconductor device with embedded heat spreading'2016 9,236,344'Thin beam deposited fuse'2016 9,224,692'Semiconductor device having a nanotube layer and method for forming'2015 9,142,507'Stress migration mitigation utilizing induced stress effects in metal trace of integrated circuit device'2015 9,134,366'Method for forming a packaged semiconductor device'2015 9,122,812'Semiconductor device with vias on a bridge connecting two buses'2015 9,122,829'Stress migration mitigation'2015 9,082,824'Method for forming an electrical connection between metal layers'2015 9,041,209'Method and apparatus to improve reliability of vias'2015 9,032,615'Method for forming an electrical connection between metal layers'2015 8,987,916'Methods and apparatus to improve reliability of isolated vias'2015 8,972,922'Method for forming an electrical connection between metal layers'2015 8,946,000'Method for forming an integrated circuit having a programmable fuse'2015 8,941,242'Method of protecting against via failure and structure therefor'2015 8,883,639'Semiconductor device having a nanotube layer and method for forming'2014 8,832,624'Multi-layer process-induced damage tracking and remediation'2014 8,796,841'Semiconductor device with embedded heat spreading'2014 8,736,071'Semiconductor device with vias on a bridge connecting two buses'2014 8,707,231'Method and system for derived layer checking for semiconductor device design'2014 8,703,507'Method and apparatus to improve reliability of vias'2014 8,694,926'Techniques for checking computer-aided design layers of a device to reduce the occurrence of missing deck rules'2014 8,640,072'Method for forming an electrical connection between metal layers'2014 8,601,430'Device matching tool and methods thereof'2013 8,595,667'Via placement and electronic circuit design processing method and electronic circuit design utilizing same'2013 8,581,390'Semiconductor device with heat dissipation'2013 8,486,839'Methods and apparatus to improve reliability of isolated vias'2013 8,039,389'Semiconductor device having an organic anti-reflective coating (ARC) and method therefor'2011 7,199,429'Semiconductor device having an organic anti-reflective coating (ARC) and method therefor'2007 6,972,255'Semiconductor device having an organic anti-reflective coating (ARC) and method therefor'2005 6,713,381'Method of forming semiconductor device including interconnect barrier layers'2004 6,597,234'Anti-fuse circuit and method of operation'2003 6,555,915'Integrated circuit having interconnect to a substrate and method therefor'2003 6,531,193'Low temperature, high quality silicon dioxide thin films deposited using tetramethylsilane (TMS) for stress control and coverage applications'2003 6,159,559'Low temperature, high quality silicon dioxide thin films deposited using tetramethylsilane (TMS)'2000 5,491,871'Solder paste and conductive ink printing stencil cleaner'1996

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1996Based in Kokomo, IN, US· patent location history

2000–2020Based in Austin, TX, US· patent location history

2005–2011Based in Saint Ismier, FR· patent location history

2007–2018Patents assigned to FREESCALE SEMICONDUCTOR INC (41)· patent assignee history

2013–2020Patents assigned to REBER DOUGLAS M (29)· patent assignee history

2013–2017Patents assigned to TRAVIS EDWARD O (20)· patent assignee history

2013–2017Patents assigned to SHROFF MEHUL D (19)· patent assignee history

2017–2020Patents assigned to NXP USA INC (16)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
FREESCALE SEMICONDUCTOR INC	41	2007–2018
REBER DOUGLAS Mself	29	2013–2020
TRAVIS EDWARD O	20	2013–2017
SHROFF MEHUL D	19	2013–2017
NXP USA INC	16	2017–2020

Locations

Location	Patents	Span
Austin, Texas, US	55	2000–2020
Saint Ismier, FR	3	2005–2011
Kokomo, IN, US	1	1996