Inventor

Manu Gulati

Inventor
Saratoga, CA, US

Overview

73→
Patents
2001–2021
Patent span
Physics
Primary field (CPC G)

Patents· 73 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing40%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use19%
H04LTransmission of digital information, e.g. telegraphic communication10%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications6%
G10LSpeech analysis techniques or speech synthesis5%
G11CStatic stores5%
G09GArrangements or circuits for control of indicating devices using static means to present variable information3%
A61GTransport, personal conveyances, or accommodation specially adapted for patients or disabled persons2%
B60PVehicles adapted for load transportation or to transport, to carry, or to comprise special loads or objects2%
G01DMeasuring not specially adapted for a specific variable2%
PatentTitleYear
11,079,261System on a chip with always-on processor202111,049,503Always-on audio control for mobile device202110,929,222Storing address of spare in failed memory location202110,884,959Way partitioning for a system-level cache202110,877,688System for managing memory devices202010,802,968Processor to memory with coherency bypass202010,795,818Method and apparatus for ensuring real-time snoop latency202010,671,762Unified addressable memory202010,573,319Always-on audio control for mobile device202010,488,230System on a chip with always-on processor201910,431,224Always-on audio control for mobile device201910,318,377Storing address of spare in failed memory location201910,310,586Memory power savings in idle display case201910,298,511Communication queue management system201910,276,165Always-on audio control for mobile device201910,261,894System on a chip with always-on processor which reconfigures SOC and supports memory-only communication mode201910,175,905Systems and methods for dynamically switching memory performance states201910,102,607Method for chaining media processing201810,079,019Always-on audio control for mobile device201810,048,720Timebase synchronization201810,042,701Storing address of spare in failed memory location201810,031,000System on a chip with always-on processor20189,959,124Secure bypass of low-level configuration in reconfiguration of a computing system20189,928,838'Clock switching in always-on component'20189,864,399'Timebase synchronization'20189,829,966Method for preparing a system for a power loss20179,811,142'Low energy processor for controlling operating states of a computer system'20179,779,468'Method for chaining media processing'20179,747,239'Transaction filter for on-chip communications network'20179,698,797'Hierarchical feedback-controlled oscillator techniques'20179,659,616'Configuration fuse data management in a partial power-on state'20179,653,079'Clock switching in always-on component'20179,632,137'Serial wire debug bridge'20179,619,377'System on a chip with always-on processor which reconfigures SOC and supports memory-only communication mode'20179,549,373'Method for waking a data transceiver through data reception'20179,529,403'Method and apparatus for providing telemetry for power management functions'20169,378,150'Memory management unit with prefetch ability'20169,280,471'Mechanism for sharing private caches in a SoC'20169,261,939'Memory power savings in idle display case'20169,229,894'Protocol conversion involving multiple virtual channels'20169,201,821'Interrupt timestamping'20159,183,147'Programmable resources to track multiple buses'20159,152,588'Race-free level-sensitive interrupt delivery using fabric delivered interrupts'20159,043,632'Security enclave processor power control'20159,009,541'Efficient trace capture buffer management'20159,009,377'Edge-triggered interrupt conversion in a system employing level-sensitive interrupts'20158,848,577'Bandwidth management'20148,832,465'Security enclave processor for a system on a chip'20148,799,715'System on a chip (SOC) debug controllability'20148,571,033'Smart routing between peers in a point-to-point link based system'20138,208,470'Connectionless packet data transport over a connection-based point-to-point link'20128,176,229'Hypertransport/SPI-4 interface supporting configurable deskewing'20127,979,573'Smart routing between peers in a point-to-point link based system'20117,680,140'Systems including packet interfaces, switches, and packet DMA circuits for splitting and merging packet streams'20107,609,718'Packet data service over hyper transport link(s)'20097,596,148'Receiving data from virtual channels'20097,551,645'Apparatus and method to receive and align incoming data including SPI data in a buffer to expand data width by utilizing a single read port and single write port memory device'20097,490,187'Hypertransport/SPI-4 interface supporting configurable deskewing'20097,424,561'Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems'20087,403,525'Efficient routing of packet data in a scalable processing resource'20087,346,078'Processing of received data within a multiple processor device'20087,319,702'Apparatus and method to receive and decode incoming data and to handle repeated simultaneous small fragments'20087,313,146'Transparent data format within host device supporting differing transaction types'20077,272,151'Centralized switching fabric scheduler supporting simultaneous updates'20077,227,870'Systems including packet interfaces, switches, and packet DMA circuits for splitting and merging packet streams'20077,206,879'Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems'20077,171,521'Coherent shared memory processing system'20076,944,719'Scalable cache coherent distributed shared memory processing system'20056,941,406'System having interfaces and switch that separates coherent and packet traffic'20056,941,440'Addressing scheme supporting variable local addressing and variable global addressing'20056,912,602'System having two or more packet interfaces, a switch, and a shared packet DMA circuit'20056,748,479'System having interfaces and switch that separates coherent and packet traffic'20046,175,911'Method and apparatus for concurrently executing multiplication and iterative operations'2001

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2001Based in Sunnyvale, CA, US· patent location history
2004–2013Patents assigned to BROADCOM CORP (23)· patent assignee history
2004–2009Based in Santa Clara, CA, US· patent location history
2005–2013Based in San Francisco, CA, US· patent location history
2012–2016Patents assigned to GULATI MANU (8)· patent assignee history
2014–2021Patents assigned to APPLE INC (48)· patent assignee history
2014–2015Patents assigned to RAMSAY JAMES D (3)· patent assignee history
2014–2021Based in Saratoga, CA, US· patent location history
2019–2020Patents assigned to Culbert Diane (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
APPLE INC482014–2021
BROADCOM CORP232004–2013
GULATI MANUself82012–2016
Culbert Diane32019–2020
RAMSAY JAMES D32014–2015
Locations
LocationPatentsSpan
Saratoga, California, US492014–2021
San Francisco, California, US122005–2013
Santa Clara, California, US112004–2009
Sunnyvale, California, US12001