Inventor
Yiheng Xu
Inventor
Hopewell Junction, NY, US
Overview
Patents· 47 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices31%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1025%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1018%
H10DInorganic electric semiconductor devices16%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation2%
H01FMagnets2%
H10KOrganic electric solid-state devices2%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems1%
G05BControl or regulating systems in general1%
PatentTitleYear
10,832,965Fin reveal forming STI regions having convex shape between fins202010,790,198Fin structures202010,700,214Overturned thin film device with self-aligned gate and source/drain (S/D) contacts202010,546,743Advanced interconnect with air gap202010,388,639Self-aligned three dimensional chip stack and method for making the same201910,361,289Gate oxide formation through hybrid methods of thermal and deposition processes and method for producing the same201910,347,617Self-aligned three dimensional chip stack and method for making the same201910,319,630Encapsulated damascene interconnect structure for integrated circuits201910,304,815Self-aligned three dimensional chip stack and method for making the same201910,211,045Microwave annealing of flowable oxides with trap layers201910,026,849Structure and process for overturned thin film device with self-aligned gate and S/D contacts20189,984,933Silicon liner for STI CMP stop in FinFET20189,905,511'Modular fuses and antifuses for integrated circuits'20189,837,394Self-aligned three dimensional chip stack and method for making the same20179,786,551'Trench structure for high performance interconnection lines of different resistivity and method of making same'20179,659,820'Interconnect structure having large self-aligned vias'20179,658,523'Interconnect structure having large self-aligned vias'20179,646,939'Multilayer structure in an integrated circuit for damage prevention and detection and methods of creating the same'20179,633,986'Technique for fabrication of microelectronic capacitors and resistors'20179,502,325'Integrated circuit barrierless microfluidic channel'20169,496,415'Structure and process for overturned thin film device with self-aligned gate and S/D contacts'20169,412,654'Graphene sacrificial deposition layer on beol copper liner-seed for mitigating queue-time issues between liner and plating step'20169,391,020'Interconnect structure having large self-aligned vias'20169,385,177'Technique for fabrication of microelectronic capacitors and resistors'20169,385,062'Integrated circuit barrierless microfluidic channel'20169,373,561'Integrated circuit barrierless microfluidic channel'20169,362,230'Methods to form conductive thin film structures'20169,337,087'Multilayer structure in an integrated circuit for damage prevention and detection and methods of creating the same'20169,324,793'Method for controlling the profile of an etched metallic layer'20169,240,375'Modular fuses and antifuses for integrated circuits'20169,214,429'Trench interconnect having reduced fringe capacitance'20159,209,036'Method for controlling the profile of an etched metallic layer'20159,082,625'Patterning through imprinting'20159,018,097'Semiconductor device processing with reduced wiring puddle formation'20159,018,092'Encapsulated metal interconnect'20158,970,004'Electrostatic discharge devices for integrated circuits'20158,921,976'Using backside passive elements for multilevel 3D wafers alignment applications'20148,900,990'System and method of combining damascenes and subtract metal etch for advanced back end of line interconnections'20148,889,506'Structure and method for interconnect spatial frequency doubling using selective ridges'20148,859,350'Recessed gate field effect transistor'20148,829,670'Through silicon via structure for internal chip cooling'20148,685,850'System and method of plating conductive gate contacts on metal gates for self-aligned contact interconnections'20148,680,577'Recessed gate field effect transistor'20148,623,673'Structure and method for detecting defects in BEOL processing'20148,395,228'Integration process to improve focus leveling within a lot process variation'20138,026,166'Interconnect structures comprising capping layers with low dielectric constants and methods of making the same'20117,570,174'Real time alarm classification and method of use'2009Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2009–2020Patents assigned to IBM (41)· patent assignee history
2009–2020Based in Hopewell Junction, NY, US· patent location history
2013–2014Patents assigned to XU YIHENG (5)· patent assignee history
2014–2020Patents assigned to ST MICROELECTRONICS INC (32)· patent assignee history
2014Patents assigned to CLEVENGER LAWRENCE A (3)· patent assignee history
2016–2020Patents assigned to GLOBALFOUNDRIES INC (6)· patent assignee history
2018–2020Based in Clifton Park, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 41 | 2009–2020 |
| ST MICROELECTRONICS INC | 32 | 2014–2020 |
| GLOBALFOUNDRIES INC | 6 | 2016–2020 |
| XU YIHENGself | 5 | 2013–2014 |
| CLEVENGER LAWRENCE A | 3 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hopewell Junction, New York, US | 42 | 2009–2020 |
| Clifton Park, New York, US | 5 | 2018–2020 |