Inventor
Scott R. Summerfelt
Inventor
Garland, TX, US
Overview
Patents· 184 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices28%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%
H10BElectronic memory devices16%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
G11CStatic stores4%
H01LSemiconductor devices3%
Y10TTechnical subjects covered by former us classification3%
H10NElectric solid-state devices not otherwise provided for2%
H01GCapacitors2%
PatentTitleYear
11,049,980Integrated MIM diode202110,911,055Oscillator self-calibration202110,873,020Piezoelectric sensing apparatus and method202010,353,503Integrated force sensing element20199,991,120Dilution doped integrated circuit resistors20189,773,793'Transistor performance modification with stressor structures'20179,619,606'Adjustable dummy fill'20179,536,822'Drawn dummy FeCAP, via and metal structures'20179,304,283'Bond-pad integration scheme for improved moisture barrier and electrical contact'20169,218,981'Hydrogen passivation of integrated circuits'20159,070,575'Integrated circuit with integrated decoupling capacitors'20159,048,297'Contact and via interconnects using metal around dielectric pillars'20159,035,458'Low resistance stacked annular contact'20158,907,446'Integrated circuit structure with capacitor and resistor and method for forming'20148,883,629'Adjustable dummy fill'20148,778,700'Hydrogen barrier for ferroelectric capacitors'20148,779,485'Hydrogen barrier for ferroelectric capacitors'20148,753,952'Integrated circuit with integrated decoupling capacitors'20148,724,367'Method and apparatus pertaining to a ferroelectric random access memory'20148,717,800'Method and apparatus pertaining to a ferroelectric random access memory'20148,669,644'Hydrogen passivation of integrated circuits'20148,658,474'Contact and via interconnects using metal around dielectric pillars'20148,659,165'Contact and VIA interconnects using metal around dielectric pillars'20148,652,855'Low resistance stacked annular contact'20148,586,130'Increasing exposure tool alignment signal strength for a ferroelectric capacitor layer'20138,508,974'Ferroelectric memory with shunt device'20138,477,522'Ferroelectric memory write-back'20138,472,236'Differential plate line screen test for ferroelectric latch circuits'20138,466,569'Increasing exposure tool alignment signal strength for a ferroelectric capacitor layer'20138,441,833'Differential plate line screen test for ferroelectric latch circuits'20138,440,508'Hydrogen barrier for ferroelectric capacitors'20138,416,598'Differential plate line screen test for ferroelectric latch circuits'20138,384,190'Passivation of integrated circuits containing ferroelectric capacitors and hydrogen barriers'20138,380,476'Modeling of ferroelectric capacitors to include local statistical variations of ferroelectric properties'20138,377,719'Drawn dummy FeCAP, via and metal structures'20138,329,588'Passivation of integrated circuits containing ferroelectric capacitors and hydrogen barriers'20128,324,742'Alignment mark for opaque layer'20128,268,696'Alignment mark for opaque layer'20128,247,855'Enhanced local interconnects employing ferroelectric electrodes'20128,093,070'Method for leakage reduction in fabrication of high-density FRAM arrays'20128,071,430'Stress buffer layer for ferroelectric random access memory'20118,058,677'Stress buffer layer for ferroelectric random access memory'20118,053,252'Mitigation of edge degradation in ferroelectric memory devices through plasma etch clean'20117,985,603'Ferroelectric capacitor manufacturing process'20117,968,974'Scribe seal connection'20117,935,543'Method of forming PZT ferroelectric capacitors for integrated circuits'20117,933,138'F-RAM device with current mirror sense amp'20117,898,837'F-SRAM power-off operation'20117,894,234'F-SRAM before package solid data write'20117,894,235'F-RAM device with current mirror sense amp'20117,889,535'F-SRAM margin screen'20117,839,670'F-RAM device with current mirror sense amp'20107,799,582'Mitigation of edge degradation in ferroelectric memory devices through plasma etch clean'20107,723,199'Method for cleaning post-etch noble metal residues'20107,572,698'Mitigation of edge degradation in ferroelectric memory devices through plasma etch clean'20097,425,512'Method for etching a substrate and a device formed using the method'20087,361,599'Integrated circuit and method'20087,250,349'Method for forming ferroelectric memory capacitor'20077,228,865'FRAM capacitor stack clean'20077,220,600'Ferroelectric capacitor stack etch cleaning methods'20077,183,602'Ferroelectric capacitor hydrogen barriers and methods for fabricating the same'20077,115,461'High permittivity silicate gate dielectric'20067,029,925'FeRAM capacitor stack etch'20067,019,352'Low silicon-hydrogen sin layer to inhibit hydrogen related degradation in semiconductor devices having ferroelectric components'20066,984,857'Hydrogen barrier for protecting ferroelectric capacitors in a semiconductor device and methods for fabricating the same'20066,982,448'Ferroelectric capacitor hydrogen barriers and methods for fabricating the same'20066,970,371'Reference generator system and methods for reading ferroelectric memory cells using reduced bitline voltages'20056,967,365'Ferroelectric memory cell with angled cell transistor active region and methods for fabricating the same'20056,911,689'Versatile system for chromium based diffusion barriers in electrode structures'20056,902,939'Integrated circuit and method'20056,876,021'Use of amorphous aluminum oxide on a capacitor sidewall for use as a hydrogen barrier'20056,872,669'PZT (111) texture through Ir texture improvement'20056,867,447'Ferroelectric memory cell and methods for fabricating the same'20056,841,396'VIA0 etch process for FRAM integration'20056,841,439'High permittivity silicate gate dielectric'20056,828,161'Method of forming an FeRAM having a multi-layer hard mask and patterning thereof'20046,819,601'Programmable reference for 1T/1C ferroelectric memories'20046,807,080'Enhanced storage states in an memory'20046,773,930'Method of forming an FeRAM capacitor having a bottom electrode diffusion barrier'20046,767,750'Detection of AIOx ears for process control in FeRAM processing'20046,734,477'Fabricating an embedded ferroelectric memory cell'20046,730,616'Versatile plasma processing system for producing oxidation resistant barriers'20046,713,342'FeRAM sidewall diffusion barrier etch'20046,709,875'Contamination control for embedded ferroelectric device fabrication processes'20046,692,976'Post-etch cleaning treatment'20046,686,236'Methods of preventing reduction of IrOx during PZT formation by metalorganic chemical vapor deposition or other processing'20046,686,210'Methods for controlling the crystallographic texture of thin films with anisotropic ferroelectric polarization or permittivity'20046,667,896'Grouped plate line drive architecture and method'20036,660,612'Design to prevent tungsten oxidation at contact alignment in FeRAM'20036,656,748'FeRAM capacitor post stack etch clean/repair'20036,635,498'Method of patterning a FeRAM capacitor with a sidewall during bottom electrode etch'20036,635,528'Method of planarizing a conductive plug situated under a ferroelectric capacitor'20036,635,497'Methods of preventing reduction of IrOx during PZT formation by metalorganic chemical vapor deposition or other processing'20036,596,547'Methods of preventing reduction of IrOx during PZT formation by metalorganic chemical vapor deposition or other processing'20036,593,638'Lightly donor doped electrodes for high-dielectric-constant materials'20036,576,482'One step deposition process for the top electrode and hardmask in a ferroelectric memory cell'20036,576,546'Method of enhancing adhesion of a conductive barrier layer to an underlying conductive plug and contact for ferroelectric applications'20036,555,431'Method for forming integrated circuit capacitor and memory'20036,548,343'Method of fabricating a ferroelectric memory cell'20036,534,809'Hardmask designs for dry etching FeRAM capacitor stacks'20036,528,328'Methods of preventing reduction of irox during PZT formation by metalorganic chemical vapor deposition or other processing'20036,528,386'Protection of tungsten alignment mark for FeRAM processing'20036,500,678'Methods of preventing reduction of IrOx during PZT formation by metalorganic chemical vapor deposition or other processing'20026,486,520'Structure and method for a large-permittivity gate using a germanium layer'20026,485,988'Hydrogen-free contact etch for ferroelectric capacitor formation'20026,462,931'High-dielectric constant capacitor and memory'20026,444,542'Integrated circuit and method'20026,441,415'Ferroelectric and paraelectric thin film devices using dopants which eliminate ferroelectricity'20026,432,473'PB substituted perovskites for thin films dielectrics'20026,362,499'Ferroelectric transistors using thin film semiconductor gate electrodes'20026,362,068'Electrode interface for high-dielectric-constant materials'20026,319,542'Lightly donor doped electrodes for high-dielectric-constant materials'20016,320,213'Diffusion barriers between noble metal electrodes and metallization layers, and integrated circuit and semiconductor devices comprising same'20016,291,282'Method of forming dual metal gate structures or CMOS devices'20016,287,903'Structure and method for a large-permittivity dielectric using a germanium layer'20016,275,370'Electrical connections to dielectric materials'20016,225,655'Ferroelectric transistors using thin film semiconductor gate electrodes'20016,215,650'Electrical connections to dielectric materials'20016,211,034'Metal patterning with adhesive hardmask layer'20016,211,035'Integrated circuit and method'20016,204,069'Lightly donor doped electrodes for high-dielectric-constant materials'20016,184,074'Method of fabrication a self-aligned polysilicon/diffusion barrier/oxygen stable sidewall bottom electrode structure for high-K DRAMS'20016,180,446'Method of fabricating an oxygen-stable layer/diffusion barrier/poly bottom electrode structure for high-K DRAMS using disposable-oxide processing'20016,177,351'Method and structure for etching a thin film perovskite layer'20016,171,898'Method of fabricating an oxygen-stable layer/diffusion barrier/poly bottom electrode structure for high-K-DRAMS using a disposable-oxide processing'20016,153,490'Method for forming integrated circuit capacitor and memory'20006,117,689'Stable high-dielectric-constant material electrode and method'20006,100,200'Sputtering process for the conformal deposition of a metallization or insulating layer'20006,087,661'Thermal isolation of monolithic thermal detector'20006,083,812'Heteroepitaxy by large surface steps'20006,033,919'Method of forming sidewall capacitance structure'20005,998,225'Method of fabricating an oxygen-stable layer/diffusion barrier/poly bottom electrode structure for high-K DRAMs using disposable-oxide processing'19995,972,722'Adhesion promoting sacrificial etch stop layer in advanced capacitor structures'19995,912,486'Pb/Bi-containing high-dielectric constant oxides using a non-Pb/Bi-containing perovskite as a buffer layer'19995,909,043'Sacrificial oxygen sources to prevent reduction of oxygen containing materials'19995,888,659'Donor doped perovskites for thin-film ferroelectric and pyroelectric devices'19995,851,896'Conductive exotic-nitride barrier layer for high-dielectric-constant material electrodes'19985,825,055'Fabricating high-dielectric constant oxides on semiconductors using a GE buffer layer'19985,811,851'Pre-oxidizing high-dielectric-constant material electrodes'19985,793,057'Conductive amorphous-nitride barrier layer for high dielectric-constant material electrodes'19985,792,377'Method and structure for forming an array of thermal sensors'19985,781,404'Electrode interface for high-dielectric-constant materials'19985,746,930'Method and structure for forming an array of thermal sensors'19985,729,054'Conductive noble-metal-insulator-alloy barrier layer for high-dielectric-constant material electrodes'19985,721,043'Method of forming improved thin film dielectrics by Pb doping'19985,696,018'Method of forming conductive noble-metal-insulator-alloy barrier layer for high-dielectric-constant material electrodes'19975,679,980'Conductive exotic-nitride barrier layer for high-dielectric-constant material electrodes'19975,665,628'Method of forming conductive amorphous-nitride barrier layer for high-dielectric-constant material electrodes'19975,656,852'High-dielectric-constant material electrodes comprising sidewall spacers'19975,654,580'Semiconductor structure for fabrication of a thermal sensor'19975,650,646'Pb/Bi-containing high-dielectric constant oxides using a non-Pb/Bi-containing perovskite as a buffer layer'19975,647,946'Structure and method including dry etching techniques for forming an array of thermal sensitive elements'19975,643,033'Method of making an anode plate for use in a field emission device'19975,638,599'Method of fabricating hybrid uncooled infrared detectors'19975,626,773'Structure and method including dry etching techniques for forming an array of thermal sensitive elements'19975,626,906'Electrodes comprising conductive perovskite-seed layers for perovskite dielectrics'19975,622,893'Method of forming conductive noble-metal-insulator-alloy barrier layer for high-dielectric-constant material electrodes'19975,619,393'High-dielectric-constant material electrodes comprising thin ruthenium dioxide layers'19975,612,574'Semiconductor structures using high-dielectric-constant materials and an adhesion layer'19975,609,927'Processing methods for high-dielectric-constant materials'19975,605,858'Method of forming high-dielectric-constant material electrodes comprising conductive sidewall spacers of same material as electrodes'19975,603,848'Method for etching through a substrate to an attached coating'19975,589,284'Electrodes comprising conductive perovskite-seed layers for perovskite dielectrics'19965,585,300'Method of making conductive amorphous-nitride barrier layer for high-dielectric-constant material electrodes'19965,581,436'High-dielectric-constant material electrodes comprising thin platinum layers'19965,576,928'High-dielectric-constant material electrodes comprising thin platinum layers'19965,566,045'High-dielectric-constant material electrodes comprising thin platinum layers'19965,554,866'Pre-oxidizing high-dielectric-constant material electrodes'19965,554,564'Pre-oxidizing high-dielectric-constant material electrodes'19965,536,965'Porous thermal isolation mesas for hybrid uncooled infrared detectors'19965,528,102'Anode plate with opaque insulating material for use in a field emission display'19965,520,992'Electrodes for high dielectric constant materials'19965,504,330'Lead substitured perovskites for thin-film pyroelectric devices'19965,504,041'Conductive exotic-nitride barrier layer for high-dielectric-constant materials'19965,489,548'Method of forming high-dielectric-constant material electrodes comprising sidewall spacers'19965,473,171'High-dielectric constant oxides on semiconductors using a Ge buffer layer'19955,471,364'Electrode interface for high-dielectric-constant materials'19955,403,437'Fluorosurfactant in photoresist for amorphous \"Teflon\" patterning'19955,393,352'Pb/Bi-containing high-dielectric constant oxides using a non-P/Bi-containing perovskite as a buffer layer'19955,348,894'Method of forming electrical connections to high dielectric constant materials'19945,326,721'Method of fabricating high-dielectric constant oxides on semiconductors using a GE buffer layer'19945,312,516'Anisotropic tantalum pentoxide etch'19945,238,530'Anisotropic titanate etch'19935,201,989'Anisotropic niobium pentoxide etch'1993Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1993–2021Patents assigned to TEXAS INSTRUMENTS INC (180)· patent assignee history
1993–2012Based in Dallas, TX, US· patent location history
1999–2021Based in Garland, TX, US· patent location history
1999–2008Based in Cupertino, CA, US· patent location history
2002–2004Patents assigned to AGILENT TECHNOLOGIES INC (17)· patent assignee history
2011–2017Patents assigned to SUMMERFELT SCOTT R (23)· patent assignee history
2012–2014Patents assigned to MOISE TED S (5)· patent assignee history
2013–2014Patents assigned to BARTLING STEVEN CRAIG (7)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TEXAS INSTRUMENTS INC | 180 | 1993–2021 |
| SUMMERFELT SCOTT Rself | 23 | 2011–2017 |
| AGILENT TECHNOLOGIES INC | 17 | 2002–2004 |
| BARTLING STEVEN CRAIG | 7 | 2013–2014 |
| MOISE TED S | 5 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Garland, Texas, US | 100 | 1999–2021 |
| Dallas, Texas, US | 69 | 1993–2012 |
| Cupertino, California, US | 15 | 1999–2008 |