Inventor
John M. Pierce
Inventor
Palo Alto, CA, US
Overview
Patents· 18 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1026%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1024%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests12%
B60RVehicles, vehicle fittings, or vehicle parts, not otherwise provided for6%
H10DInorganic electric semiconductor devices6%
B24BMachines, devices, or processes for grinding or polishing3%
B60NSeats specially adapted for vehicles3%
C03CChemical composition of glasses, glazes or vitreous enamels3%
C23CCoating metallic material3%
C23FNon-mechanical removal of metallic material from surface3%
PatentTitleYear
6,948,645'Adjustable frame for retaining hand truck on vehicular body'20056,786,373'Adjustable frame for retaining hand truck on vehicular body'20046,406,093'Attachment for seat assembly'20026,008,107'Method of planarizing integrated circuits with fully recessed isolation dielectric'19995,883,010'Method for protecting nonsilicided surfaces from silicide formation using spacer oxide mask'19995,589,412'Method of making increased-density flash EPROM that utilizes a series of planarized, self-aligned, intermediate strips of conductive material to contact the drain regions'19965,422,289'Method of manufacturing a fully planarized MOSFET and resulting structure'19955,302,551'Method for planarizing the surface of an integrated circuit over a metal interconnect layer'19945,287,663'Polishing pad and method for polishing semiconductor wafers'19945,094,972'Means of planarizing integrated circuits with fully recessed isolation dielectric'19924,727,048'Process for making isolated semiconductor structure'19884,630,343'Product for making isolated semiconductor structure'19864,619,844'Method and apparatus for low pressure chemical vapor deposition'19864,489,482'Impregnation of aluminum interconnects with copper'19844,490,737'Smooth glass insulating film over interconnects on an integrated circuit'19844,352,239'Process for suppressing electromigration in conducting lines formed on integrated circuits by control of crystalline boundary orientation'19824,267,012'Process for patterning metal connections on a semiconductor structure by using a tungsten-titanium etch resistant layer'19814,221,834'Superconductive magnetic shield and method of making same'1980Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1980Patents assigned to DEVELCO (1)· patent assignee history
1980–1999Based in Palo Alto, CA, US· patent location history
1981–1988Patents assigned to FAIRCHILD CAMERA INSTR CO (6)· patent assignee history
1982Patents assigned to FAIRCHILD CAMERA AND INSTR (1)· patent assignee history
1992–1999Patents assigned to NAT SEMICONDUCTOR CORP (7)· patent assignee history
2002Based in Clarkston, MI, US· patent location history
2004–2005Patents assigned to MICKEY TRUCK BODIES INC (2)· patent assignee history
2004–2005Based in High Point, NC, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NAT SEMICONDUCTOR CORP | 7 | 1992–1999 |
| FAIRCHILD CAMERA INSTR CO | 6 | 1981–1988 |
| MICKEY TRUCK BODIES INC | 2 | 2004–2005 |
| DEVELCO | 1 | 1980 |
| FAIRCHILD CAMERA AND INSTR | 1 | 1982 |
Locations
| Location | Patents | Span |
|---|---|---|
| Palo Alto, California, US | 15 | 1980–1999 |
| High Point, NC, US | 2 | 2004–2005 |
| Clarkston, MI, US | 1 | 2002 |