Inventor

Yai-Fen Lin

Inventor

Taichung, TW

Overview

1999–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 68 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices42%

H10BElectronic memory devices39%

G11CStatic stores8%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%

B29CShaping or joining of plastics1%

H01LSemiconductor devices1%

PatentTitleYear

11,024,618Wafer-level underfill and over-molding2021 7,417,278'Method to increase coupling ratio of source to floating gate in split-gate flash'2008 7,001,809'Method to increase coupling ratio of source to floating gate in split-gate flash'2006 6,753,569'Method to fabricate a non-smiling effect structure in split-gate flash with self-aligned isolation'2004 6,724,036'Stacked-gate flash memory cell with folding gate and increased coupling ratio'2004 6,674,118'PIP capacitor for split-gate flash process'2004 6,667,509'Method of forming sharp beak of poly by oxygen/fluorine implant to improve erase speed for split-gate flash'2003 6,635,922'Method to fabricate poly tip in split gate flash'2003 6,573,555'Source side injection programming and tip erasing P-channel split gate flash memory cell'2003 6,538,277'Split-gate flash cell'2003 6,534,821'Structure with protruding source in split-gate flash'2003 6,509,603'P-channel EEPROM and flash EEPROM devices'2003 6,504,206'Split gate flash cell for multiple storage'2003 6,483,159'Undoped polysilicon as the floating-gate of a split-gate flash cell'2002 6,465,841'Split gate flash memory device having nitride spacer to prevent inter-poly oxide damage'2002 6,455,887'Nonvolatile devices with P-channel EEPROM device as injector'2002 6,441,429'Split-gate flash memory device having floating gate electrode with sharp peak'2002 6,417,049'Split gate flash cell for multiple storage'2002 6,410,957'Method of forming poly tip to improve erasing and programming speed in split gate flash'2002 6,396,112'Method of fabricating buried source to shrink chip size in memory array'2002 6,385,089'Split-gate flash cell for virtual ground architecture'2002 6,380,583'Method to increase coupling ratio of source to floating gate in split-gate flash'2002 6,380,035'Poly tip formation and self-align source process for split-gate flash cell'2002 6,358,796'Method to fabricate a non-smiling effect structure in split-gate flash with self-aligned isolation'2002 6,355,527'Method to increase coupling ratio of source to floating gate in split-gate flash'2002 6,344,997'Split-gate flash cell for virtual ground architecture'2002 6,333,228'Method to improve the control of bird\'s beak profile of poly in split gate flash'2001 6,326,660'Method to improve the capacity of data retention and increase the coupling ratio of source to floating gate in split-gate flash'2001 6,312,989'Structure with protruding source in split-gate flash'2001 6,309,928'Split-gate flash cell'2001 6,277,686'PIP capacitor for split-gate flash process'2001 6,259,131'Poly tip and self aligned source for split-gate flash cell'2001 6,249,454'Split-gate flash cell for virtual ground architecture'2001 6,246,089'P-channel EEPROM devices'2001 6,242,308'Method of forming poly tip to improve erasing and programming speed split gate flash'2001 6,229,176'Split gate flash with step poly to improve program speed'2001 6,228,695'Method to fabricate split-gate with self-aligned source and self-aligned floating gate to control gate'2001 6,214,662'Forming self-align source line for memory array'2001 6,207,515'Method of fabricating buried source to shrink chip size in memory array'2001 6,207,503'Method for shrinking array dimensions of split gate flash memory device using multilayer etching to define cell and source line'2001 6,188,103'Method of forming sharp beak of poly by nitrogen implant to improve erase speed for split-gate flash'2001 6,180,977'Self-aligned edge implanted cell to reduce leakage current and improve program speed in split-gate flash'2001 6,174,772'Optimal process flow of fabricating nitride spacer without inter-poly oxide damage in split gate flash'2001 6,171,906'Method of forming sharp beak of poly to improve erase speed in split gate flash'2001 6,165,845'Method to fabricate poly tip in split-gate flash'2000 6,159,801'Method to increase coupling ratio of source to floating gate in split-gate flash'2000 6,153,494'Method to increase the coupling ratio of word line to floating gate by lateral coupling in stacked-gate flash'2000 6,130,132'Clean process for manufacturing of split-gate flash memory device having floating gate electrode with sharp peak'2000 6,127,229'Process of forming an EEPROM device having a split gate'2000 6,124,609'Split gate flash memory with buried source to shrink cell dimension and increase coupling ratio'2000 6,121,088'Method of manufacture of undoped polysilicon as the floating-gate of a split-gate flash cell'2000 6,117,733'Poly tip formation and self-align source process for split-gate flash cell'2000 6,093,608'Source side injection programming and tip erasing P-channel split gate flash memory cell'2000 6,093,607'Method of forming sharp beak of poly by oxygen/fluorine implant to improve erase speed for split-gate flash'2000 6,090,668'Method to fabricate sharp tip of poly in split gate flash'2000 6,067,254'Method to avoid program disturb and allow shrinking the cell size in split gate flash memory'2000 6,060,360'Method of manufacture of P-channel EEprom and flash EEprom devices'2000 6,046,086'Method to improve the capacity of data retention and increase the coupling ratio of source to floating gate in split-gate flash'2000 6,017,795'Method of fabricating buried source to shrink cell dimension and increase coupling ratio in split-gate flash'2000 6,005,809'Program and erase method for a split gate flash EEPROM'1999 5,976,927'Two mask method for reducing field oxide encroachment in memory arrays'1999 5,972,753'Method of self-align cell edge implant to reduce leakage current and improve program speed in split-gate flash'1999 5,970,371'Method of forming sharp beak of poly to improve erase speed in split-gate flash EEPROM'1999 5,950,087'Method to make self-aligned source etching available in split-gate flash'1999 5,940,706'Process for preventing misalignment in split-gate flash memory cell'1999 5,933,732'Nonvolatile devices with P-channel EEPROM devices as injector'1999 5,879,992'Method of fabricating step poly to improve program speed in split gate flash'1999 5,858,840'Method of forming sharp beak of poly by nitrogen implant to improve erase speed for split-gate flash'1999

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1999–2008Patents assigned to TAIWAN SEMICONDUCTOR MFG (67)· patent assignee history

1999–2003Based in Taichung, TW· patent location history

2000–2006Based in Non-Tour, TW· patent location history

2000–2008Based in Hsingchu, TW· patent location history

2001–2003Based in Hsinchu, TW· patent location history

2021Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (1)· patent assignee history

2021Based in Caotun Township, TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TAIWAN SEMICONDUCTOR MFG	67	1999–2008
TAIWAN SEMICONDUCTOR MFG CO LTD	1	2021

Locations

Location	Patents	Span
Taichung, TW	35	1999–2003
Non-Tour, TW	19	2000–2006
Hsinchu, TW	7	2001–2003
Hsingchu, TW	3	2000–2008
Caotun Township, TW	1	2021