Inventor
David G. Farber
Inventor
Plano, TX, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1029%
H10DInorganic electric semiconductor devices19%
H01LSemiconductor devices17%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%
H01JElectric discharge tubes or discharge lamps7%
G06FElectric digital data processing5%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%
H10NElectric solid-state devices not otherwise provided for2%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
PatentTitleYear
10,453,700Low damage low-k dielectric etch20199,881,795'Method of fabricating semiconductors'20189,704,720'Uniform, damage free nitride ETCH'20179,490,143'Method of fabricating semiconductors'20169,437,449'Uniform, damage free nitride etch'20169,224,657'Hard mask for source/drain epitaxy control'20159,054,158'Method of forming a metal contact opening with a width that is smaller than the minimum feature size of a photolithographically-defined opening'20158,665,592'Heat management using power management information'20148,564,120'Heat dissipation in temperature critical device areas of semiconductor devices by heat pipes connecting to the substrate backside'20138,507,386'Lateral uniformity in silicon recess etch'20138,064,197'Heat management using power management information'20117,745,337'Method of optimizing sidewall spacer size for silicide proximity with in-situ clean'20107,741,663'Air gap spacer formation'20107,687,407'Method for reducing line edge roughness for conductive features'20107,112,288'Methods for inspection sample preparation'20067,087,518'Method of passivating and/or removing contaminants on a low-k dielectric/copper surface'20066,780,756'Etch back of interconnect dielectrics'20046,245,686'Process for forming a semiconductor device and a process for operating an apparatus'20016,232,134'Method and apparatus for monitoring wafer characteristics and/or semiconductor processing consistency using wafer charge distribution measurements'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2014Based in Austin, TX, US· patent location history
2004–2019Patents assigned to TEXAS INSTRUMENTS INC (12)· patent assignee history
2004–2010Based in Wylie, TX, US· patent location history
2010–2013Patents assigned to GLOBALFOUNDRIES INC (3)· patent assignee history
2011–2014Patents assigned to ADVANCED MICRO DEVICES INC (2)· patent assignee history
2011–2014Patents assigned to AUSTIN MICHAEL J (2)· patent assignee history
2011–2014Patents assigned to FARBER DAVID G (2)· patent assignee history
2013–2019Based in Plano, TX, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TEXAS INSTRUMENTS INC | 12 | 2004–2019 |
| GLOBALFOUNDRIES INC | 3 | 2010–2013 |
| ADVANCED MICRO DEVICES INC | 2 | 2011–2014 |
| AUSTIN MICHAEL J | 2 | 2011–2014 |
| FARBER DAVID Gself | 2 | 2011–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Plano, Texas, US | 8 | 2013–2019 |
| Austin, Texas, US | 7 | 2001–2014 |
| Wylie, Texas, US | 4 | 2004–2010 |