Inventor
Dustin J. VanStee
Inventor
Poughkeepsie, NY, US
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing50%
G11CStatic stores32%
G01RMeasuring electric variables5%
H04LTransmission of digital information, e.g. telegraphic communication5%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications3%
PatentTitleYear
10,658,059Performance evaluation of solid state memory device20209,524,800'Performance evaluation of solid state memory device'20169,495,289'Solid state memory device logical and physical partitioning'20169,495,287'Solid state memory device logical and physical partitioning'20169,159,458'Flash interface error injector'20159,047,988'Flash interface error injector'20159,015,537'Bit error rate based wear leveling for solid state drive memory'20159,003,068'Service channel for connecting a host computer to peripheral devices'20158,832,506'Bit error rate based wear leveling for solid state drive memory'20148,639,874'Power management of a spare DRAM on a buffered DIMM by issuing a power on/off command to the DRAM device'20148,627,158'Flash array built in self test engine with trace array and flash metric reporting'20148,214,580'Solid state drive with adjustable drive life and capacity'20128,015,426'System and method for providing voltage power gating'20117,984,222'Systems for providing performance monitoring in a memory system'20117,979,616'System and method for providing a configurable command sequence for a memory interface device'20117,954,021'Solid state drive with flash sparing'20117,669,086'Systems and methods for providing collision detection in a memory system'20107,624,225'System and method for providing synchronous dynamic random access memory (SDRAM) mode register shadowing in a memory system'20097,606,988'Systems and methods for providing a dynamic memory bank page policy'20097,603,526'Systems and methods for providing dynamic memory pre-fetch'20097,493,439'Systems and methods for providing performance monitoring in a memory system'20097,290,159'Fixed latency data computation and chip crossing circuits and methods for synchronous input to output protocol translator supporting multiple reference oscillator frequencies'20077,181,659'Memory built-in self test engine apparatus and method with trigger on failure and multiple patterns per load capability'20076,807,650'DDR-II driver impedance adjustment control algorithm and interface circuits'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2020Patents assigned to IBM (24)· patent assignee history
2004–2020Based in Poughkeepsie, NY, US· patent location history
2012–2015Patents assigned to VANSTEE DUSTIN J (4)· patent assignee history
2012–2014Patents assigned to TRESSLER GARY A (2)· patent assignee history
2012Based in Poughkeespie, NY, US· patent location history
2014–2015Patents assigned to GRIFFIN THOMAS J (3)· patent assignee history
2014–2015Patents assigned to CADIGAN DAVID D (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 24 | 2004–2020 |
| VANSTEE DUSTIN Jself | 4 | 2012–2015 |
| GRIFFIN THOMAS J | 3 | 2014–2015 |
| CADIGAN DAVID D | 2 | 2014–2015 |
| TRESSLER GARY A | 2 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Poughkeepsie, New York, US | 23 | 2004–2020 |
| Poughkeespie, New York, US | 1 | 2012 |