Inventor

Wei-E Wang

Inventor

Austin, TX, US

Overview

20→

Patents

2013–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 20 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary

H01LSemiconductor devices32%

H10DInorganic electric semiconductor devices32%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1025%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%

H10BElectronic memory devices3%

B82YSpecific uses or applications of nanostructures2%

PatentTitleYear

10,854,591Semiconductor device including a repeater/buffer at upper metal routing layers and methods of manufacturing the same2020 10,770,353Method of forming multi-threshold voltage devices using dipole-high dielectric constant combinations and devices so formed2020 10,727,297Complimentary metal-oxide-semiconductor circuit having transistors with different threshold voltages and method of manufacturing the same2020 10,586,738Method of providing source and drain doping for CMOS architecture including FinFET and semiconductor devices so formed2020 10,475,930Method of forming crystalline oxides on III-V materials2019 10,446,400Method of forming multi-threshold voltage devices and devices so formed2019 10,026,751Semiconductor device including a repeater/buffer at higher metal routing layers and methods of manufacturing the same2018 10,026,652Horizontal nanosheet FETs and method of manufacturing the same2018 9,941,405Nanosheet and nanowire devices having source/drain stressors and methods of manufacturing the same2018 9,905,672'Method of forming internal dielectric spacers for horizontal nanosheet FET architectures'2018 9,870,940'Methods of forming nanosheets on lattice mismatched substrates'2018 9,812,449'Multi-VT gate stack for III-V nanosheet devices with reduced parasitic capacitance'2017 9,793,403'Multi-layer fin field effect transistor devices and methods of forming the same'2017 9,773,906'Relaxed semiconductor layers with reduced defects and methods of forming the same'2017 9,698,234'Interface layer for gate stack using O3 post treatment'2017 9,691,860'Methods of forming defect-free SRB onto lattice-mismatched substrates and defect-free fins on insulators'2017 9,343,303'Methods of forming low-defect strain-relaxed layers on lattice-mismatched substrates and related semiconductor structures and devices'2016 9,218,964'Antiphase domain boundary-free III-V compound semiconductor material on semiconductor substrate and method for manufacturing thereof'2015 9,064,699'Methods of forming semiconductor patterns including reduced dislocation defects and devices formed using such methods'2015 8,524,562'Method for reducing Fermi-Level-Pinning in a non-silicon channel MOS device'2013

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2013–2017Patents assigned to WANG WEI-E (6)· patent assignee history

2013–2015Patents assigned to IMEC (2)· patent assignee history

2013–2015Based in Overijse, BE· patent location history

2015–2020Patents assigned to SAMSUNG ELECTRONICS CO LTD (18)· patent assignee history

2015–2017Patents assigned to RODDER MARK S (3)· patent assignee history

2015–2017Patents assigned to BOWEN ROBERT C (2)· patent assignee history

2015–2020Based in Austin, TX, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
SAMSUNG ELECTRONICS CO LTD	18	2015–2020
WANG WEI-Eself	6	2013–2017
RODDER MARK S	3	2015–2017
BOWEN ROBERT C	2	2015–2017
IMEC	2	2013–2015

Locations

Location	Patents	Span
Austin, Texas, US	18	2015–2020
Overijse, BE	2	2013–2015