Inventor
Manabu Iguchi
Inventor
Kanagawa, JP
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1050%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1025%
H01LSemiconductor devices8%
H10DInorganic electric semiconductor devices6%
C23CCoating metallic material3%
H01JElectric discharge tubes or discharge lamps3%
H10BElectronic memory devices3%
Y10TTechnical subjects covered by former us classification3%
PatentTitleYear
9,337,093'Method of manufacturing semiconductor device'20168,946,800'Semiconductor device with protective layer and method of manufacturing same'20158,487,305'Semiconductor device and method of manufacturing the same'20138,329,584'Method of manufacturing semiconductor device'20128,158,446'Semiconductor device and method of manufacturing the same'20127,955,980'Method of manufacturing semiconductor device'20117,601,640'Method of manfacturing semiconductor device'20097,358,609'Semiconductor device'20087,138,700'Semiconductor device with guard ring for preventing water from entering circuit region from outside'20067,052,994'Method for manufacturing semiconductor device, and processing system and semiconductor device'20067,019,400'Semiconductor device having multilayer interconnection structure and method for manufacturing the device'20066,876,064'Semiconductor device having superior resistance to moisture'20056,861,759'Semiconductor apparatus of which reliability of interconnections is improved and manufacturing method of the same'20056,841,880'Semiconductor device and method of fabricating semiconductor device with high CMP uniformity and resistance to loss that occurs in dicing'20056,555,911'Semiconductor device and method of manufacturing interconnections thereof using copper and tungsten in predetermined ratios'20036,458,690'Method for manufacturing a multilayer interconnection structure'20026,379,782'Semiconductor device formed with metal wiring on a wafer by chemical mechanical polishing, and method of manufacturing the same'20026,376,363'Forming method of copper interconnection and semiconductor wafer with copper interconnection formed thereon'20026,225,697'Semiconductor device and method for manufacturing the same'20016,149,730'Apparatus for forming films of a semiconductor device, a method of manufacturing a semiconductor device, and a method of forming thin films of a semiconductor'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2002Patents assigned to NEC CORP (5)· patent assignee history
2000–2006Based in Tokyo, JP· patent location history
2003–2009Patents assigned to NEC ELECTRONICS CORP (9)· patent assignee history
2005–2016Based in Kanagawa, JP· patent location history
2005–2015Based in Kawasaki, JP· patent location history
2011–2016Patents assigned to RENESAS ELECTRONICS CORP (6)· patent assignee history
2012–2016Patents assigned to IGUCHI MANABU (5)· patent assignee history
2015–2016Patents assigned to INOUE NAOYA (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NEC ELECTRONICS CORP | 9 | 2003–2009 |
| RENESAS ELECTRONICS CORP | 6 | 2011–2016 |
| IGUCHI MANABUself | 5 | 2012–2016 |
| NEC CORP | 5 | 2000–2002 |
| INOUE NAOYA | 2 | 2015–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Kanagawa, JP | 10 | 2005–2016 |
| Tokyo, JP | 7 | 2000–2006 |
| Kawasaki, JP | 3 | 2005–2015 |