LexDanaLexDanabeta
Inventor

Brian J. Campbell

Inventor
Sunnyvale, CA, US

Overview

49→
Patents
1999–2019
Patent span
Physics
Primary field (CPC G)

Patents· 49 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores32%
H03KPulse technique31%
G01RMeasuring electric variables10%
G06FElectric digital data processing10%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%
A01NPreservation of bodies of humans or animals or plants or parts thereof4%
B60DVehicle connections3%
B60QArrangement of signalling or lighting devices, the mounting or supporting thereof or circuits therefor, for vehicles in general3%
Y02ATechnologies for adaptation to climate change3%
PatentTitleYear
10,490,265Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage201910,482,952Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage201910,470,466Anthroquinone containing derivatives as biochemical agricultural products20199,672,901'Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage'20179,380,778'Anthroquinone containing derivatives as biochemical agricultural products'20169,343,139'Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage'20169,129,708'Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage'20158,848,463'Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage'20148,625,368'Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage'20148,553,488'Performing stuck-at testing using multiple isolation circuits'20138,476,930'Level shifter with embedded logic and low minimum voltage'20138,416,635'Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage'20138,395,954'Leakage and NBTI reduction technique for memory'20138,341,578'Clock gater with test features and low setup time'20128,289,785'Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage'20128,286,987'Animated novelty device'20128,219,755'Fast hit override'20128,203,898'Leakage and NBTI reduction technique for memory'20128,171,326'L1 flush mechanism to flush cache for power down and handle coherence during flush and/or after power down'20128,102,728'Cache optimizations using multiple threshold voltage transistors'20128,098,534'Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage'20128,091,915'Animated novelty device'20128,015,356'Fast hit override'20117,994,820'Level shifter with embedded logic and low minimum voltage'20117,995,410'Leakage and NBTI reduction technique for memory'20117,915,920'Low latency, power-down safe level shifter'20117,834,662'Level shifter with embedded logic and low minimum voltage'20107,779,372'Clock gater with test features and low setup time'20107,760,559'Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage'20107,752,474'L1 cache flush when processor is entering low power mode'20107,652,504'Low latency, power-down safe level shifter'20107,474,571'Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage'20097,355,905'Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage'20087,218,562'Recovering bit lines in a memory array after stopped clock operation'20077,129,755'High-fanin static multiplexer'20066,995,586'Monotonic leakage-tolerant logic circuits'20066,989,691'Dynamic to static converter with noise suppression'20066,950,973'Dynamic scan circuitry for A-phase'20056,925,590'Scan interface'20056,859,402'Circuit for lines with multiple drivers'20056,822,482'Dynamic scan circuitry for B-phase'20046,784,715'Conditional clock buffer circuit'20046,717,442'Dynamic to static converter with noise suppression'20046,686,775'Dynamic scan circuitry for B-phase'20046,674,671'Circuit for lines with multiple drivers'20046,639,443'Conditional clock buffer circuit'20036,630,856'High-speed bank select multiplexer latch'20036,522,189'High-speed bank select multiplexer latch'20035,994,266'Ultra violet radiation lignin protected pesticidal compositions'1999

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1999Based in Seattle, WA, US· patent location history
2003–2006Patents assigned to BROADCOM CORP (14)· patent assignee history
2003–2013Based in Sunnyvale, CA, US· patent location history
2010–2019Patents assigned to APPLE INC (27)· patent assignee history
2010–2019Based in Cupertino, CA, US· patent location history
2012–2013Patents assigned to CAMPBELL BRIAN J (13)· patent assignee history
2012–2013Patents assigned to HESS GREG M (4)· patent assignee history
2012–2013Patents assigned to MURRAY DANIEL C (4)· patent assignee history
2012Based in Clermont, FL, US· patent location history
2016–2019Based in Davis, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
APPLE INC272010–2019
BROADCOM CORP142003–2006
CAMPBELL BRIAN Jself132012–2013
HESS GREG M42012–2013
MURRAY DANIEL C42012–2013
Locations
LocationPatentsSpan
Sunnyvale, California, US262003–2013
Cupertino, California, US182010–2019
Davis, California, US22016–2019
Clermont, Florida, US22012
Seattle, Washington, US11999