Inventor
Josephus C. Ebergen
Inventor
San Francisco, CA, US
Overview
Patents· 28 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing63%
H04LTransmission of digital information, e.g. telegraphic communication13%
H03KPulse technique10%
G05BControl or regulating systems in general7%
G01RMeasuring electric variables3%
H04BTransmission3%
PatentTitleYear
10,467,139Fault-tolerant cache coherence over a lossy network201910,452,547Fault-tolerant cache coherence over a lossy network201910,423,389Methods for constructing lookup tables for division and square-root implementations201910,353,670Floating point unit with support for variable length numbers201910,289,386Iterative division with reduced latency20199,747,073'Floating point unit with support for variable length numbers'20179,298,421'Performing quotient selection for a carry-save division operation'20169,218,157'Performing a division operation using a split division circuit'20158,977,663'Converting binary values into binary-coded-centimal values'20158,930,582'Method and apparatus for regulating communications between multiple transmitters and receivers'20158,222,924'Asynchronous FIFO circuit for long-distance on-chip communication'20128,027,425'Asynchronous loadable down counter'20117,890,826'Method and apparatus for test of asynchronous pipelines'20117,660,842'Method and apparatus for performing a carry-save division operation'20107,417,993'Apparatus and method for high-throughput asynchronous communication'20087,256,628'Speed-matching control method and circuit'20077,139,786'Method and apparatus for efficiently performing a square root operation'20066,954,772'Method and apparatus for performing modular division'20056,917,957'Method and apparatus for performing modular division using counters'20056,892,278'Method and apparatus for efficiently implementing a last-in first-out buffer'20056,772,243'Apparatus and method for generating a partial fullness indicator signal in a FIFO'20046,707,317'Method and apparatus for asynchronously controlling domino logic gates'20046,700,825'Implementation of a multi-dimensional, low latency, first-in first-out (FIFO) buffer'20046,629,301'Determining transistor widths using the theory of logical effort'20036,486,721'Latch control circuit for crossing clock domains'20026,486,709'Distributing data to multiple destinations within an asynchronous circuit'20026,420,907'Method and apparatus for asynchronously controlling state information within a circuit'20026,356,117'Asynchronously controlling data transfers within a circuit'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2010Patents assigned to SUN MICROSYSTEMS INC (15)· patent assignee history
2002–2019Based in San Francisco, CA, US· patent location history
2011–2015Patents assigned to ORACLE AMERICA INC (4)· patent assignee history
2012–2015Patents assigned to EBERGEN JOSEPHUS C (3)· patent assignee history
2012Patents assigned to COATES WILLIAM S (1)· patent assignee history
2015–2019Patents assigned to ORACLE INT CORP (9)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SUN MICROSYSTEMS INC | 15 | 2002–2010 |
| ORACLE INT CORP | 9 | 2015–2019 |
| ORACLE AMERICA INC | 4 | 2011–2015 |
| EBERGEN JOSEPHUS Cself | 3 | 2012–2015 |
| COATES WILLIAM S | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Francisco, California, US | 28 | 2002–2019 |