LexDanaLexDanabeta
Inventor

Atul Katoch

Inventor
Kanata, CA

Overview

57→
Patents
2007–2021
Patent span
Physics
Primary field (CPC G)

Patents· 57 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores77%
G06FElectric digital data processing8%
H03KPulse technique7%
H04LTransmission of digital information, e.g. telegraphic communication3%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems2%
H03MCoding2%
H10DInorganic electric semiconductor devices2%
PatentTitleYear
11,031,063Word-line driver and method of operating a word-line driver202110,984,854Memory device with signal edge sharpener circuitry202110,923,182Fixed-level charge sharing type LCV for memory compiler202110,923,184Dual rail SRAM device202110,878,867Memory cell distance tracking circuits and methods202010,789,994Memory architecture having first and second voltages202010,783,938SRAM with local bit line, input/output circuit, and global bit line202010,770,122Memory input hold time adjustment202010,705,934Scan synchronous-write-through testing architectures for a memory device202010,699,766Word-line driver and method of operating a word-line driver202010,522,202Memory device and compensation method therein201910,515,690Memory architecture and method of access thereto201910,475,502Word-line driver and method of operating a word-line driver201910,468,075Memory architecture having first and second voltages201910,163,477Memory array having disturb detector and write assistor201810,157,664Memory controlling device by using multi-phase control signal and method thereof20189,984,765Memory circuit with assist circuit trimming20189,940,988Method of controlling a wordline20189,916,874'Memory architecture having first and second voltages'20189,881,655'Memory circuit having data lines selectively coupled to a sense amplifier and method for operating the same'20189,824,780'Memory device with redundant IO circuit'20179,805,779'Writing to multi-port memories'20179,704,599'Memory circuit with assist circuit trimming'20179,679,636'Memory architecture'20179,508,451'Detecting write disturb in multi-port memories'20169,443,574'Memory architecture'20169,390,787'Biasing bulk of a transistor'20169,367,662'Fault injection of finFET devices'20169,355,697'Wordline driver'20169,324,412'Memory architecture'20169,324,415'Clamping circuit for multiple-port memory cell'20169,311,968'Read tracking mechanism'20169,305,623'Write assist circuit for write disturbed memory cell'20169,270,262'Power management during wakeup'20169,183,947'Detecting write disturb in multi-port memories'20159,177,631'Memory circuit with switch between sense amplifier and data line and method for operating the same'20159,019,782'Dual rail memory architecture'20159,013,940'Sense amplifier'20158,959,468'Fault injection of finFET devices'20158,929,160'Tracking circuit'20158,873,321'Boosting supply voltage'20148,861,295'Memory circuits, systems, and methods for accessing the memory circuits'20148,681,576'Pre-charge and equalization devices'20148,675,433'Sense amplifier'20148,619,483'Memory circuits, systems, and methods for accessing the memory circuits'20138,619,462'VSS-sensing amplifier'20138,605,529'Sense amplifiers and exemplary applications'20138,581,658'Charge pump'20138,509,018'Sense amplifier with adjustable back bias'20138,295,112'Sense amplifiers and exemplary applications'20128,238,141'VSS-sensing amplifier'20127,616,051'Integrated circuit, electronic device and integrated circuit control method'20097,605,740'Flash analog-to-digital converter'20097,439,759'Operating long on-chip buses'20087,429,885'Clamping circuit to counter parasitic coupling'20087,355,443'Integrated circuit having building blocks'20087,212,034'Current mode signaling in electronic data processing circuit'2007

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2007–2008Based in Eindhoven, NL· patent location history
2008–2016Patents assigned to KATOCH ATUL (15)· patent assignee history
2009–2021Based in Kanata, CA· patent location history
2012–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (25)· patent assignee history
2012–2014Patents assigned to O'CONNELL CORMAC MICHAEL (5)· patent assignee history
2012–2016Patents assigned to TAYAL MAYANK (4)· patent assignee history
2012Based in Ontario, CA· patent location history
2016–2021Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (26)· patent assignee history
2020–2021Based in Hsinchu, TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TAIWAN SEMICONDUCTOR MFG CO LTD262016–2021
TAIWAN SEMICONDUCTOR MFG252012–2016
KATOCH ATULself152008–2016
O'CONNELL CORMAC MICHAEL52012–2014
TAYAL MAYANK42012–2016
Locations
LocationPatentsSpan
Kanata, CA492009–2021
Eindhoven, NL42007–2008
Hsinchu, TW32020–2021
Ontario, CA12012