Inventor
Sarma Vrudhula
Inventor
Chandler, AZ, US
Overview
Patents· 18 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing28%
H03KPulse technique28%
G11CStatic stores13%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use9%
G01RMeasuring electric variables3%
G05DSystems for controlling or regulating non-electric variables3%
G06NComputing arrangements based on specific computational models3%
H01LSemiconductor devices3%
H10NElectric solid-state devices not otherwise provided for3%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications3%
PatentTitleYear
10,795,809Non-volatile logic device for energy-efficient logic state restoration202010,551,869Clock skewing strategy to reduce dynamic power and eliminate hold-time violations in synchronous digital VLSI designs202010,447,249Hold violation free scan chain and scanning mechanism for testing of synchronous digital VLSI circuits201910,250,236Energy efficient, robust differential mode d-flip-flop201910,133,323Processor control system20189,934,463Neuromorphic computational system(s) using resistive synaptic devices20189,933,825Determining parameters that affect processor energy efficiency20189,876,503Method of obfuscating digital logic circuits using threshold voltage20189,490,815'Robust, low power, reconfigurable threshold logic array'20169,473,139'Threshold logic element with stabilizing feedback'20169,466,362'Resistive cross-point architecture for robust data representation with arbitrary precision'20169,356,598'Threshold logic gates with resistive networks'20169,306,151'Threshold gate and threshold logic array'20168,832,614'Technology mapping for threshold and logic gate hybrid circuits'20148,601,417'Decomposition based approach for the synthesis of threshold logic circuits'20138,181,133'Combinational equivalence checking for threshold logic circuits'20128,164,359'Threshold logic element having low leakage power and high performance'20127,630,852'Method of evaluating integrated circuit system performance using orthogonal polynomials'2009Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2009–2016Patents assigned to UNIV ARIZONA (6)· patent assignee history
2009–2020Based in Chandler, AZ, US· patent location history
2012–2020Patents assigned to VRUDHULA SARMA (13)· patent assignee history
2014–2020Patents assigned to KULKARNI NIRANJAN (7)· patent assignee history
2016–2020Patents assigned to UNIV ARIZONA STATE (9)· patent assignee history
2018–2020Patents assigned to DENGI AYKUT (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| VRUDHULA SARMAself | 13 | 2012–2020 |
| UNIV ARIZONA STATE | 9 | 2016–2020 |
| KULKARNI NIRANJAN | 7 | 2014–2020 |
| UNIV ARIZONA | 6 | 2009–2016 |
| DENGI AYKUT | 3 | 2018–2020 |
Locations
| Location | Patents | Span |
|---|---|---|
| Chandler, AZ, US | 18 | 2009–2020 |