LexDanaLexDanabeta
Inventor

Toshiyuki Takewaki

Inventor
Kanagawa, JP

Overview

52→
Patents
1999–2019
Patent span
Electricity
Primary field (CPC H)

Patents· 52 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1043%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1022%
H10DInorganic electric semiconductor devices13%
H01LSemiconductor devices11%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
H10BElectronic memory devices3%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications2%
Y10TTechnical subjects covered by former us classification1%
PatentTitleYear
10,410,868Semiconductor device and method of manufacturing semiconductor device20199,984,884Method of manufacturing semiconductor device with a multi-layered gate dielectric20189,812,398'Semiconductor memory device having memory cells provided in a height direction'20179,666,597'Semiconductor memory device'20179,660,045'Semiconductor device and a method for manufacturing a semiconductor device'20179,559,183'Semiconductor device with varying thickness of insulating film between electrode and gate electrode and method of manufacturing semiconductor device'20179,443,868'Semiconductor memory device and method of manufacturing the same'20169,362,401'Semiconductor device'20169,306,027'Semiconductor device and a method for manufacturing a semiconductor device'20169,177,857'Semiconductor device with high reliability and manufacturing method thereof'20159,070,661'Semiconductor device including a strain relaxation film'20158,642,467'Semiconductor device having silicon-diffused metal wiring layer and its manufacturing method'20148,486,836'Semiconductor device and method of manufacturing the same'20138,487,442'Semiconductor device having dual damascene structure'20138,329,584'Method of manufacturing semiconductor device'20128,115,318'Semiconductor device having silicon-diffused metal wiring layer and its manufacturing method'20128,053,863'Electrical fuse and semiconductor device'20118,030,737'Semiconductor device and method of manufacturing the same'20117,955,980'Method of manufacturing semiconductor device'20117,936,072'Semiconductor device having dual damascene structure'20117,897,475'Semiconductor device having projection on lower electrode and method for forming the same'20117,888,254'Semiconductor device having a refractory metal containing film and method for manufacturing the same'20117,846,830'Semiconductor device and method for manufacturing same'20107,842,602'Semiconductor device having silicon-diffused metal wiring layer and its manufacturing method'20107,821,101'Semiconductor device including capacitor including upper electrode covered with high density insulation film and production method thereof'20107,745,937'Semiconductor device and method of manufacturing the same'20107,741,214'Method of forming a semiconductor device featuring copper wiring layers of different widths having metal capping layers of different thicknesses formed thereon'20107,737,555'Semiconductor method having silicon-diffused metal wiring layer'20107,728,432'Narrow and wide copper interconnections composed of (111), (200) and (511) surfaces'20107,692,265'Fuse and seal ring'20107,687,917'Single damascene structure semiconductor device having silicon-diffused metal wiring layer'20107,674,704'Method of manufacturing a semiconductor device having an interconnect structure that increases in impurity concentration as width increases'20107,633,138'Semiconductor device and method of manufacturing the same'20097,601,640'Method of manfacturing semiconductor device'20097,521,802'Semiconductor device having a refractory metal containing film and method for manufacturing the same'20097,514,352'Method of manufacturing a semiconductor device having an interconnect structure that increases in impurity concentration as width increases'20097,508,082'Semiconductor device and method of manufacturing the same'20097,479,700'Semiconductor device featuring copper wiring layers of different widths having metal capping layers of different thickness formed thereon, and method for manufacturing the same'20097,476,611'Semiconductor device and manufacturing method thereof'20097,358,609'Semiconductor device'20087,327,031'Semiconductor device and method of manufacturing the same'20087,312,535'Semiconductor device having an anti-oxidizing layer that inhibits corrosion of an interconnect layer'20077,274,104'Semiconductor device having an interconnect that increases in impurity concentration as width increases'20077,229,921'Semiconductor device and manufacturing method for the same'20077,052,994'Method for manufacturing semiconductor device, and processing system and semiconductor device'20066,949,832'Semiconductor device including dissimilar element-diffused metal layer and manufacturing method thereof'20056,890,864'Semiconductor device fabricating method and treating liquid'20056,555,911'Semiconductor device and method of manufacturing interconnections thereof using copper and tungsten in predetermined ratios'20036,458,690'Method for manufacturing a multilayer interconnection structure'20026,391,774'Fabrication process of semiconductor device'20026,379,782'Semiconductor device formed with metal wiring on a wafer by chemical mechanical polishing, and method of manufacturing the same'20025,874,777'Semiconductor device with enhanced thermal conductivity'1999

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1999Based in Miyagi, JP· patent location history
2002Patents assigned to NEC CORP (3)· patent assignee history
2002–2019Based in Tokyo, JP· patent location history
2003–2010Patents assigned to NEC ELECTRONICS CORP (25)· patent assignee history
2005–2016Based in Kanagawa, JP· patent location history
2008–2017Based in Kawasaki, JP· patent location history
2010–2019Patents assigned to RENESAS ELECTRONICS CORP (20)· patent assignee history
2012–2015Patents assigned to TAKEWAKI TOSHIYUKI (6)· patent assignee history
2012–2014Patents assigned to OHTO KOICHI (3)· patent assignee history
2016–2017Based in Yokkaichi, JP· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
NEC ELECTRONICS CORP252003–2010
RENESAS ELECTRONICS CORP202010–2019
TAKEWAKI TOSHIYUKIself62012–2015
NEC CORP32002
OHTO KOICHI32012–2014
Locations
LocationPatentsSpan
Kanagawa, JP262005–2016
Kawasaki, JP132008–2017
Tokyo, JP92002–2019
Yokkaichi, JP32016–2017
Miyagi, JP11999