Inventor
Chung-Yi Yu
Inventor
Hsinchu, TW
Overview
Patents· 104 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices26%
H01LSemiconductor devices23%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
H10BElectronic memory devices6%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation5%
H10HInorganic light-emitting semiconductor devices having potential barriers2%
H10NElectric solid-state devices not otherwise provided for2%
G11CStatic stores2%
B81BMicrostructural devices or systems, e.g. micromechanical devices1%
PatentTitleYear
10,865,103Packaging method and associated packaging structure202010,867,792High electron mobility transistor (HEMT) having an indium-containing layer and method of manufacturing the same202010,861,896Capping structure to reduce dark current in image sensors202010,833,026Integrated circuit with backside structures to reduce substrate warp202010,804,101Semiconductor structure having sets of III-V compound layers and method of forming202010,777,649Silicon nano-tip thin film for flash memory cells202010,497,860Perpendicular magnetic random-access memory (MRAM) formation by direct self-assembly method201910,497,560Uniformity control for Si dot size in flash memory201910,483,386Semiconductor device, transistor having doped seed layer and method of manufacturing the same201910,468,486SOI substrate, semiconductor device and method for manufacturing the same201910,351,418Bond rings in semiconductor devices and methods of forming same201910,294,098Method for manufacturing a MEMS device by first hybrid bonding a CMOS wafer to a MEMS wafer201910,276,513Integrated circuit with backside structures to reduce substrate warp201910,164,038Method of implanting dopants into a group III-nitride structure and device formed201810,157,994High electron mobility transistor and method of forming the same201810,109,736Superlattice buffer structure for gallium nitride transistors201810,109,729High electron mobility transistors201810,079,296High electron mobility transistor with indium nitride layer201810,074,537Method of forming semiconductor structure having sets of III-V compound layers201810,014,402High electron mobility transistor (HEMT) device structure20189,957,156Bond rings in semiconductor devices and methods of forming same20189,929,007'e-Flash Si dot nitrogen passivation for trap reduction'20189,899,493'High electron mobility transistor and method of forming the same'20189,876,093High electron mobility transistor and method of forming the same20189,818,858'Multi-layer active layer having a partial recess'20179,741,800'III-V multi-channel FinFETs'20179,685,518'Method of forming semiconductor structure of control gate, and semiconductor device'20179,660,063'Semiconductor structure having sets of III-V compound layers and method of forming the same'20179,646,938'Integrated circuit with backside structures to reduce substrate warp'20179,634,105'Silicon nano-tip thin film for flash memory cells'20179,627,243'Method and apparatus of holding a device'20179,620,362'Seed layer structure for growth of III-V materials on silicon'20179,577,077'Well controlled conductive dot size in flash memory'20179,570,431'Semiconductor wafer for integrated packages'20179,548,376'Method of manufacturing a semiconductor device including a barrier structure'20179,525,054'High electron mobility transistor and method of forming the same'20169,478,632'Method of manufacturing a semiconductor device'20169,455,341'Transistor having a back-barrier layer and method of making the same'20169,425,276'High electron mobility transistors'20169,401,434'E-flash cell band engineering for erasing speed enhancement'20169,385,136'Silicon dot formation by self-assembly method and selective silicon growth for flash memory'20169,373,689'High electron mobility transistor and method of forming the same'20169,368,610'High electron mobility transistor with indium nitride layer'20169,281,203'Silicon dot formation by direct self-assembly method for flash memory'20169,257,636'Perpendicular magnetic random-access memory (MRAM) formation by direct self-assembly method'20169,245,991'Semiconductor device, high electron mobility transistor (HEMT) and method of manufacturing'20169,236,464'Method of forming a high electron mobility transistor'20169,236,465'High electron mobility transistor and method of forming the same'20169,233,844'Graded aluminum—gallium—nitride and superlattice buffer layer for III-V nitride layer on silicon substrate'20169,224,847'High electron mobility transistor and method of forming the same'20159,209,190'Deep trench capacitor'20159,202,875'High electron mobility transistor with indium nitride layer'20159,184,041'Integrated circuit with backside structures to reduce substrate warp'20159,153,435'Reducing wafer distortion through a high CTE layer'20159,142,407'Semiconductor structure having sets of III-V compound layers and method of forming the same'20159,123,671'Silicon wafer strength enhancement'20159,099,388'III-V multi-channel FinFETs'20159,093,511'Transistor having high breakdown voltage and method of making the same'20159,076,854'Semiconductor device'20159,064,821'Silicon dot formation by self-assembly method and selective silicon growth for flash memory'20158,975,641'Transistor having an ohmic contact by gradient layer and method of making the same'20158,969,882'Transistor having an ohmic contact by screen layer and method of making the same'20158,912,570'High electron mobility transistor and method of forming the same'20148,901,609'Transistor having doped substrate and method of making the same'20148,895,992'High electron mobility transistor and method of forming the same'20148,884,268'Diffusion barrier layer for group III nitride on silicon substrate'20148,878,318'Structure and method for a MRAM device with an oxygen absorbing cap layer'20148,866,192'Semiconductor device, high electron mobility transistor (HEMT) and method of manufacturing'20148,851,133'Method and apparatus of holding a device'20148,809,910'Thick AlN inter-layer for III-nitride layer on silicon substrate'20148,809,976'Method and structure for a MRAM device with a bilayer passivation'20148,809,179'Method for reducing topography of non-volatile memory and resulting memory cells'20148,803,158'High electron mobility transistor and method of forming the same'20148,791,504'Substrate breakdown voltage improvement for group III-nitride on a silicon substrate'20148,790,954'Method of making wafer structure for backside illuminated color image sensor'20148,772,845'Technique for smoothing an interface between layers of a semiconductor device'20148,772,831'III-nitride growth method on silicon substrate'20148,723,185'Reducing wafer distortion through a high CTE layer'20148,710,560'Embedded bonding pad for image sensors'20148,629,037'Forming a protective film on a back side of a silicon wafer in a III-V family fabrication process'20148,629,531'Structure and method to reduce wafer warp for gallium nitride on silicon wafer'20148,629,013'Junction leakage reduction through implantation'20148,624,326'FinFET device and method of manufacturing same'20148,525,286'Method of making wafer structure for backside illuminated color image sensor'20138,476,146'Reducing wafer distortion through a low CTE layer'20138,383,440'Light shield for CMOS imager'20138,344,343'Composite film for phase change memory devices'20138,334,187'Hard mask for thin film resistor manufacture'20128,173,518'Method of wafer bonding'20128,080,461'Method of making a thin film resistor'20117,935,994'Light shield for CMOS imager'20117,906,418'Semiconductor device having substantially planar contacts and body'20117,799,654'Reduced refractive index and extinction coefficient layer for enhanced photosensitivity'20107,786,552'Semiconductor device having hydrogen-containing layer'20107,667,261'Split-gate memory cells and fabrication methods thereof'20107,652,318'Split-gate memory cells and fabrication methods thereof'20107,638,852'Method of making wafer structure for backside illuminated color image sensor'20097,544,982'Image sensor device suitable for use with logic-embedded CIS chips and methods for making the same'20097,326,588'Image sensor with light guides'20087,199,001'Method of forming MIM capacitor electrodes'20077,153,744'Method of forming self-aligned poly for embedded flash'20066,969,899'Image sensor with light guides'20056,780,731'HDP gap-filling process for structures with extra step at side-wall'20046,653,203'Thin sidewall multi-step HDP deposition method to achieve completely filled high aspect ratio trenches'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (56)· patent assignee history
2003–2020Based in Hsinchu, TW· patent location history
2011–2016Patents assigned to YU CHUNG-YI (26)· patent assignee history
2012–2015Patents assigned to TSAI CHIA-SHIUNG (12)· patent assignee history
2013–2016Patents assigned to CHEN CHI-MING (12)· patent assignee history
2015–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (47)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 56 | 2003–2016 |
| TAIWAN SEMICONDUCTOR MFG CO LTD | 47 | 2015–2020 |
| YU CHUNG-YIself | 26 | 2011–2016 |
| CHEN CHI-MING | 12 | 2013–2016 |
| TSAI CHIA-SHIUNG | 12 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 104 | 2003–2020 |