Inventor
Chirag S. Patel
Inventor
Peekskill, NY, US
Overview
Patents· 47 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1036%
LOC1212%
G02BOptical elements, systems or apparatus6%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
B60NSeats specially adapted for vehicles5%
B64DEquipment for fitting in or to aircraft5%
H10DInorganic electric semiconductor devices5%
G01RMeasuring electric variables4%
Y02TClimate change mitigation technologies related to transportation4%
B23KSoldering or unsoldering2%
PatentTitleYear
9,656,583'Passenger seat'20179,159,616'Silicon carrier space transformer and temporary chip attach burn-in vehicle for high density connections'20158,827,365'Passenger seat'20148,755,644'Silicon based optical vias'20148,733,840'Seat pan assembly'2014D0684507'Vehicle rear tow cover'20138,439,435'Passenger seat'20138,405,226'Semiconductor device and method of making semiconductor device'20138,328,156'Techniques for forming solder bump interconnects'2012D0671454'Vehicle exterior'2012D0671049'Vehicle bumper unit'2012D0671048'Vehicle bumper'2012D0671050'Vehicle bumper garnish'2012D0671051'Vehicle bumper garnish'20128,310,259'Silicon carrier space transformer and temporary chip attach burn-in vehicle for high density connections'20128,295,056'Silicon carrier structure and method of forming same'20128,290,008'Silicon carrier optoelectronic packaging'20128,222,079'Semiconductor device and method of making semiconductor device'20128,173,541'Chip carrier substrate including capacitor and method for fabrication thereof'20128,148,255'Techniques for forming solder bump interconnects'20128,143,726'Semiconductor device and method of making semiconductor device'20128,097,492'Method and manufacture of silicon based package and devices manufactured thereby'20127,948,077'Integrated circuit chip module with microchannel cooling device having specific fluid channel arrangement'20117,888,786'Electronic module comprising memory and integrated circuit processor chips formed on a microchannel cooling device'20117,855,442'Silicon based package'20107,820,521'Conductive through via structure and process for electronic device carriers'20107,808,798'Versatile Si-based packaging with integrated passive components for mmWave applications'2010D0619525'Wheel'2010D0619069'Wheel'20107,719,079'Chip carrier substrate capacitor and method for fabrication thereof'2010D0615023'Vehicle center console receptacle'2010D0592585'Vehicle ceiling console'20097,518,225'Chip system architecture for performance enhancement, power reduction and cost reduction'20097,518,229'Versatile Si-based packaging with integrated passive components for mmWave applications'20097,488,680'Conductive through via process for electronic device carriers'20097,456,046'Method to create flexible connections for integrated circuits'20087,352,066'Silicon based optical vias'20087,276,787'Silicon chip carrier with conductive through-vias and method for fabricating same'20077,230,334'Semiconductor integrated circuit chip packages having integrated microchannel cooling modules'20077,189,595'Method of manufacture of silicon based package and devices manufactured thereby'20077,132,736'Devices having compliant wafer-level packages with pillars and methods of fabrication'20067,033,927'Apparatus and method for thermal isolation, circuit cooling and electromagnetic shielding of a wafer'20066,972,243'Fabrication of semiconductor dies with micro-pins and structures produced therewith'20056,954,576'Guided-wave optical interconnections embedded within a microelectronic wafer-level batch package'20056,785,458'Guided-wave optical interconnections embedded within a microelectronic wafer-level batch package'20046,690,081'Compliant wafer-level packaging devices and methods of fabrication'20046,528,349'Monolithically-fabricated compliant wafer-level package with wafer level reliability and functionality testability'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2015Based in Peekskill, NY, US· patent location history
2004–2006Based in College Park, GA, US· patent location history
2005–2015Patents assigned to IBM (28)· patent assignee history
2009–2013Patents assigned to HONDA MOTOR CO LTD (10)· patent assignee history
2009–2010Based in Long Beach, CA, US· patent location history
2012–2015Patents assigned to PATEL CHIRAG S (12)· patent assignee history
2012–2014Patents assigned to PATEL CHIRAG (9)· patent assignee history
2012–2013Patents assigned to DAVIDSON BENJAMIN (6)· patent assignee history
2012–2017Based in Dallas, TX, US· patent location history
2012Based in Yorktown Heights, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 28 | 2005–2015 |
| PATEL CHIRAG Sself | 12 | 2012–2015 |
| HONDA MOTOR CO LTD | 10 | 2009–2013 |
| PATEL CHIRAGself | 9 | 2012–2014 |
| DAVIDSON BENJAMIN | 6 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Peekskill, New York, US | 28 | 2003–2015 |
| Dallas, Texas, US | 10 | 2012–2017 |
| Long Beach, California, US | 4 | 2009–2010 |
| College Park, Georgia, US | 3 | 2004–2006 |
| Yorktown Heights, New York, US | 1 | 2012 |