LexDanaLexDanabeta
Inventor

Chih-Yuh Yang

Inventor
San Jose, CA, US

Overview

71→
Patents
1999–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 71 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1034%
H10DInorganic electric semiconductor devices32%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
H10BElectronic memory devices8%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices4%
H01LSemiconductor devices2%
G02BOptical elements, systems or apparatus1%
G11CStatic stores1%
PatentTitleYear
10,622,370System and method for manufacturing self-aligned STI with single poly20209,276,007'System and method for manufacturing self-aligned STI with single poly'20169,245,895'Oro and orpro with bit line trench to suppress transport program disturb'20168,642,441'Self-aligned STI with single poly for manufacturing a flash memory device'20148,012,830'ORO and ORPRO with bit line trench to suppress transport program disturb'20117,951,675'SI trench between bitline HDP for BVDSS improvement'20117,915,160'Methods for forming small contacts'20117,867,848'Methods for fabricating dual bit flash memory devices'20117,732,281'Methods for fabricating dual bit flash memory devices'20107,696,038'Methods for fabricating flash memory devices'20107,675,104'Integrated circuit memory system employing silicon rich layers'20107,268,066'Method for semiconductor gate line dimension reduction'20077,183,223'Methods for forming small contacts'20077,183,152'Epitaxially grown fin for FinFET'20077,029,959'Source and drain protection and stringer-free gate formation in semiconductor devices'20067,029,958'Self aligned damascene gate'20067,005,386'Method for reducing resist height erosion in a gate etch process'20066,960,804'Semiconductor device having a gate structure surrounding a fin'20056,913,958'Method for patterning a feature using a trimmed hardmask'20056,905,971'Treatment of dielectric material to enhance etch rate'20056,864,556'CVD organic polymer film for advanced gate patterning'20056,849,530'Method for semiconductor gate line dimension reduction'20056,835,618'Epitaxially grown fin for FinFET'20046,828,259'Enhanced transistor gate using E-beam radiation'20046,797,552'Method for defect reduction and enhanced control over critical dimensions and profiles in semiconductor devices'20046,790,782'Process for fabrication of a transistor gate including high-K gate dielectric with in-situ resist trim, gate etch, and high-K dielectric removal'20046,787,854'Method for forming a fin in a finFET device'20046,787,476'Etch stop layer for etching FinFET gate over a large topography'20046,773,998'Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning'20046,764,947'Method for reducing gate line deformation and reducing gate line widths in semiconductor devices'20046,764,966'Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric'20046,764,949'Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication'20046,750,127'Method for fabricating a semiconductor device using amorphous carbon having improved etch resistance'20046,740,566'Ultra-thin resist shallow trench process using high selectivity nitride etch'20046,653,735'CVD silicon carbide layer as a BARC and hard mask for gate patterning'20036,653,231'Process for reducing the critical dimensions of integrated circuit device features'20036,645,797'Method for forming fins in a FinFET device using sacrificial carbon layer'20036,630,288'Process for forming sub-lithographic photoresist features by modification of the photoresist surface'20036,606,738'Analytical model for predicting the operating process window for lithographic patterning techniques based on photoresist trim technology'20036,599,766'Method for determining an anti reflective coating thickness for patterning a thin film semiconductor layer'20036,589,709'Process for preventing deformation of patterned photoresist features'20036,579,809'In-situ gate etch process for fabrication of a narrow gate transistor structure with a high-k gate dielectric'20036,566,230'Shallow trench isolation spacer for weff improvement'20036,563,183'Gate array with multiple dielectric properties and method for forming same'20036,544,885'Polished hard mask process for conductor layer patterning'20036,514,871'Gate etch process with extended CD trim capability'20036,451,647'Integrated plasma etch of gate and gate dielectric and low power plasma post gate etch removal of high-K residual'20026,440,640'Thin resist with transition metal hard mask for via etch application'20026,323,093'Process for fabricating a semiconductor device component by oxidizing a silicon hard mask'20016,309,926'Thin resist with nitride hard mask for gate etch application'20016,306,560'Ultra-thin resist and SiON/oxide hard mask for metal etch'20016,287,918'Process for fabricating a metal semiconductor device component by lateral oxidization'20016,214,683'Process for fabricating a semiconductor device component using lateral metal oxidation'20016,211,044'Process for fabricating a semiconductor device component using a selective silicidation reaction'20016,200,884'Method for shaping photoresist mask to improve high aspect ratio ion implantation'20016,200,907'Ultra-thin resist and barrier metal/oxide hard mask for metal etch'20016,184,128'Method using a thin resist mask for dual damascene stop layer etch'20016,171,763'Ultra-thin resist and oxide/nitride hard mask for metal etch'20016,165,695'Thin resist with amorphous silicon hard mask for via etch application'20006,162,587'Thin resist with transition metal hard mask for via etch application'20006,156,658'Ultra-thin resist and silicon/oxide hard mask for metal etch'20006,140,023'Method for transferring patterns created by lithography'20006,133,129'Method for fabricating a metal structure with reduced length that is beyond photolithography limitations'20006,127,070'Thin resist with nitride hard mask for via etch application'20006,121,155'Integrated circuit fabrication critical dimension control using self-limiting resist etch'20006,107,172'Controlled linewidth reduction during gate pattern formation using an SiON BARC'20006,103,611'Methods and arrangements for improved spacer formation within a semiconductor device'20006,060,377'Method for fabricating a polysilicon structure with reduced length that is beyond photolithography limitations'20006,020,269'Ultra-thin resist and nitride/oxide hard mask for metal etch'20005,990,524'Silicon oxime spacer for preventing over-etching during local interconnect formation'19995,965,461'Controlled linewidth reduction during gate pattern formation using a spin-on barc'1999

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1999–2010Patents assigned to ADVANCED MICRO DEVICES INC (61)· patent assignee history
1999–2020Based in San Jose, CA, US· patent location history
2010–2016Patents assigned to SPANSION LLC (8)· patent assignee history
2014–2016Patents assigned to CHANG KUO-TUNG (2)· patent assignee history
2014–2016Patents assigned to YANG CHIH-YUH (2)· patent assignee history
2016Patents assigned to CYPRESS SEMICONDUCTOR CORP (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
ADVANCED MICRO DEVICES INC611999–2010
SPANSION LLC82010–2016
CHANG KUO-TUNG22014–2016
CYPRESS SEMICONDUCTOR CORP22016
YANG CHIH-YUHself22014–2016
Locations
LocationPatentsSpan
San Jose, California, US711999–2020