Inventor

Ching-Huang Lu

Inventor

Fremont, CA, US

Overview

2013–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 61 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores24%

H10BElectronic memory devices20%

H01LSemiconductor devices19%

H10DInorganic electric semiconductor devices14%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%

G11BInformation storage based on relative movement between record carrier and transducer2%

Y10TTechnical subjects covered by former us classification2%

H04RLoudspeakers, microphones, gramophone pick-ups or like acoustic electromechanical transducers1%

B81BMicrostructural devices or systems, e.g. micromechanical devices1%

PatentTitleYear

10,878,914Memory device with compensation for program speed variations due to block oxide thinning2020 10,854,300Multi-state programming in memory device with loop-dependent bit line voltage during verify2020 10,811,109Multi-pass programming process for memory device which omits verify test in first program pass2020 10,804,282Three-dimensional memory devices using carbon-doped aluminum oxide backside blocking dielectric layer for etch resistivity enhancement and methods of making the same2020 10,762,973Suppressing program disturb during program recovery in memory device2020 10,741,253Memory device with compensation for erase speed variations due to blocking oxide layer thinning2020 10,706,941Multi-state programming in memory device with loop-dependent bit line voltage during verify2020 10,692,877Non-volatile memory with silicided bit line contacts2020 10,685,979Three-dimensional memory device with drain-select-level isolation structures and method of making the same2020 10,685,978Three-dimensional memory device with drain-select-level isolation structures and method of making the same2020 10,665,299Memory device with channel discharge before program-verify based on data state and sub-block position2020 10,665,301Memory device with compensation for program speed variations due to block oxide thinning2020 10,665,313Detecting short circuit between word line and source line in memory device and recovery method2020 10,636,501Memory device with reduced neighbor word line interference using adjustable voltage on source-side unselected word line2020 10,629,272Two-stage ramp up of word line voltages in memory device to suppress read disturb2020 10,629,616Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer2020 10,566,059Three dimensional NAND memory device with drain select gate electrode shared between multiple strings2020 10,541,035Read bias adjustment for compensating threshold voltage shift due to lateral charge movement2020 10,510,413Multi-pass programming with modified pass voltages to tighten threshold voltage distributions2019 10,482,981Preventing refresh of voltages of dummy memory cells to reduce threshold voltage downshift for select gate transistors2019 10,446,244Adjusting voltage on adjacent word line during verify of memory cells on selected word line in multi-pass programming2019 10,373,697Programming dummy memory cells in erase operation to reduce threshold voltage downshift for select gate transistors2019 10,276,248Early ramp down of dummy word line voltage during read to suppress select gate transistor downshift2019 10,256,137Self-aligned trench isolation in integrated circuits2019 10,249,372Reducing hot electron injection type of read disturb in 3D memory device during signal switching transients2019 10,235,294Pre-read voltage pulse for first read error handling2019 10,204,689Non-volatile memory with methods to reduce creep-up field between dummy control gate and select gate2019 10,121,552Reducing charge loss in data memory cell adjacent to dummy memory cell2018 10,115,464Electric field to reduce select gate threshold voltage shift2018 10,115,737Charge storage region in non-volatile memory2018 10,068,651Channel pre-charge to suppress disturb of select gate transistors during erase in memory2018 10,020,314Forming memory cell film in stack opening2018 10,008,271Programming of dummy memory cell to reduce charge loss in select gate transistor2018 9,899,410'Charge storage region in non-volatile memory'2018 9,852,803Dummy word line control scheme for non-volatile memory2017 9,830,963Word line-dependent and temperature-dependent erase depth2017 9,831,114Self-aligned trench isolation in integrated circuits2017 9,831,118Reducing neighboring word line in interference using low-k oxide2017 9,779,948'Method of fabricating 3D NAND'2017 9,761,320'Reducing hot electron injection type of read disturb during read recovery phase in 3D memory'2017 9,748,266'Three-dimensional memory device with select transistor having charge trapping gate dielectric layer and methods of making and operating thereof'2017 9,728,551'Multi-tier replacement memory stack structure integration scheme'2017 9,673,216'Method of forming memory cell film'2017 9,666,591'Non-volatile memory with silicided bit line contacts'2017 9,530,785'Three-dimensional memory devices having a single layer channel and methods of making thereof'2016 9,520,146'Method of forming a fully wrapped-around shielded PMR writer pole'2016 9,443,861'Fluorine-blocking insulating spacer for backside contact structure of three-dimensional memory structures'2016 9,437,305'Programming memory with reduced short-term charge loss'2016 9,437,470'Self-aligned trench isolation in integrated circuits'2016 9,406,387'Charge redistribution during erase in charge trapping memory'2016 9,378,832'Method to recover cycling damage and improve long term data retention'2016 9,324,439'Weak erase after programming to improve data retention in charge-trapping memory'2016 9,312,010'Programming of drain side word line to reduce program disturb and charge loss'2016 9,257,191'Charge redistribution during erase in charge trapping memory'2016 9,252,154'Non-volatile memory with silicided bit line contacts'2016 9,252,026'Buried trench isolation in integrated circuits'2016 9,230,663'Programming memory with reduced short-term charge loss'2016 8,914,969'Method for providing a monolithic shield for a magnetic recording transducer'2014 8,866,213'Non-Volatile memory with silicided bit line contacts'2014 8,533,937'Method of forming a fully wrapped-around shielded PMR writer pole'2013 8,518,832'Process for masking and removal of residue from complex shapes'2013

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2013–2014Patents assigned to WESTERN DIGITAL FREMONT LLC (3)· patent assignee history

2013–2020Based in Fremont, CA, US· patent location history

2014–2016Patents assigned to SPANSION LLC (3)· patent assignee history

2016–2020Patents assigned to SANDISK TECHNOLOGIES LLC (44)· patent assignee history

2016–2017Patents assigned to SANDISK TECHNOLOGIES INC (11)· patent assignee history

2016–2020Patents assigned to CYPRESS SEMICONDUCTOR CORP (7)· patent assignee history

2017Based in San Jose, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
SANDISK TECHNOLOGIES LLC	44	2016–2020
SANDISK TECHNOLOGIES INC	11	2016–2017
CYPRESS SEMICONDUCTOR CORP	7	2016–2020
SPANSION LLC	3	2014–2016
WESTERN DIGITAL FREMONT LLC	3	2013–2014

Locations

Location	Patents	Span
Fremont, California, US	60	2013–2020
San Jose, California, US	1	2017