Inventor
Steven K. Hsu
Inventor
Lake Oswego, OR, US
Overview
Patents· 54 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Kprimary
H03KPulse technique41%
G11CStatic stores30%
G01RMeasuring electric variables11%
G06FElectric digital data processing3%
H05KPrinted circuits3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
C25DProcesses for the electrolytic or electrophoretic production of coatings1%
G06KGraphical data reading1%
H01RElectrically-conductive connections1%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses1%
PatentTitleYear
10,862,462Vectored flip-flop202010,756,736Fused voltage level shifting latch202010,498,314Vectored flip-flop201910,491,217Low-power clock gate circuit201910,473,718Multibit vectored sequential with scan201910,418,975Low clock supply voltage interruptible sequential201910,382,019Time borrowing flip-flop with clock gating scan multiplexer201910,193,536Shared keeper and footer flip-flop201910,177,765Integrated clock gate circuit with embedded NOR201910,049,724Aging tolerant register file20189,985,612Time borrowing flip-flop with clock gating scan multiplexer20189,960,753Apparatus and method for low power fully-interruptible latches and master-slave flip-flops20189,859,876'Shared keeper and footer flip-flop'20189,641,160'Common N-well state retention flip-flop'20179,397,641'Apparatus and method for low power fully-interruptible latches and master-slave flip-flops'20169,059,715'Voltage level shift with interim-voltage-controlled contention interrupt'20159,035,686'Apparatus and method for low power fully-interruptible latches and master-slave flip-flops'20158,265,135'Method and apparatus for video processing'20128,078,662'Multiplier product generation based on encoded data from addressable location'20117,855,575'Wide voltage range level shifter with symmetrical switching'20107,838,424'Enhanced reliability of wafer-level chip-scale packaging (WLCSP) die separation using dry etching'20107,800,407'Multiple voltage mode pre-charging and selective level shifting'20107,642,129'Ball-mounting method for coplanarity improvement in large package'20107,606,062'Ultra low voltage and minimum operating voltage tolerant register file'20097,426,127'Full-rail, dual-supply global bitline accelerator CAM circuit'20087,379,491'Flop repeater circuit'20087,372,763'Memory with spatially encoded data storage'20087,362,621'Register file with a selectable keeper circuit'20087,352,209'Voltage-level converter'20087,332,937'Dynamic logic with adaptive keeper'20087,272,029'Transition-encoder sense amplifier'20077,250,783'Current mirror multi-channel leakage current monitor circuit and method'20077,209,395'Low leakage and leakage tolerant stack free multi-ported register file'20077,161,826'Low-noise leakage-tolerant register file technique'20077,132,856'Hybrid CVSL pass-gate level-converting sequential circuit for multi-Vcc microprocessors'20067,099,219'Multi read port bit line'20067,057,913'Low-power search line circuit encoding technique for content addressable memories'20067,016,239'Leakage tolerant register file'20067,002,375'Robust variable keeper strength process-compensated dynamic circuit and method'20066,878,260'Process for forming a high-quality interface between a plated and a non-plated area'20056,844,750'Current mirror based multi-channel leakage current monitor circuit and method'20056,781,892'Active leakage control in single-ended full-swing caches'20046,762,957'Low clock swing latch for dual-supply voltage design'20046,749,465'Card connector with reinforcing structure'20046,707,708'Static random access memory with symmetric leakage-compensated bit line'20046,693,461'Multiple supply-voltage zipper CMOS logic family with low active leakage power dissipation'20046,690,604'Register files and caches with digital sub-threshold leakage current calibration'20046,643,199'Memory with reduced sub-threshold leakage current in dynamic bit lines of read ports'20036,628,143'Full-swing source-follower leakage tolerant dynamic logic'20036,628,557'Leakage-tolerant memory arrangements'20036,618,316'Pseudo-static single-ended cache cell'20036,563,357'Level converting latch'20036,441,648'Double data rate dynamic logic'20026,404,234'Variable virtual ground domino logic with leakage control'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2020Patents assigned to INTEL CORP (50)· patent assignee history
2002–2020Based in Lake Oswego, OR, US· patent location history
2004–2005Patents assigned to HTC CORP (2)· patent assignee history
2004–2005Based in Taoyuan, TW· patent location history
2010Based in Chung-Ho, TW· patent location history
2011–2016Patents assigned to HSU STEVEN K (3)· patent assignee history
2011–2012Patents assigned to KRISHNAMURTHY RAM (2)· patent assignee history
2012–2016Patents assigned to AGARWAL AMIT (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 50 | 2002–2020 |
| AGARWAL AMIT | 3 | 2012–2016 |
| HSU STEVEN Kself | 3 | 2011–2016 |
| HTC CORP | 2 | 2004–2005 |
| KRISHNAMURTHY RAM | 2 | 2011–2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Lake Oswego, OR, US | 50 | 2002–2020 |
| Chung-Ho, TW | 2 | 2010 |
| Taoyuan, TW | 2 | 2004–2005 |