Inventor
HOSADURGA SHOBHA
Inventor
US
Overview
Patents· 29 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices36%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1036%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
H10DInorganic electric semiconductor devices6%
C23CCoating metallic material3%
B05DProcesses for applying fluent materials to surfaces, in general1%
B82YSpecific uses or applications of nanostructures1%
G01BMeasuring length, thickness or similar linear dimensions1%
G01NInvestigating or analysing materials by determining their chemical or physical properties1%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
PatentTitleYear
12,598,983Interconnects formed using integrated damascene and subtractive etch processing202612,588,261Selective deposition on metals using porous low-k materials202612,575,400Power planes and pass-through vias202612,550,713Hybrid buried power rail structure with dual front side and backside processing202612,538,553Contact structure for power delivery on semiconductor device202612,494,408Double patterned microcooler having alternating fin widths202512,424,557Dual structured buried rail202512,424,549Skip-level TSV with hybrid dielectric scheme for backside power delivery202512,417,963Isolation rail between backside power rails202512,417,926Circuit interconnect structure202512,412,836Backside power plane202512,334,442Dielectric caps for power and signal line routing202512,334,398Multilayer dielectric stack for damascene top-via integration202512,266,607Bottom barrier free interconnects without voids202512,261,056Top via patterning using metal as hard mask and via conductor202512,218,003Selective ILD deposition for fully aligned via with airgap202512,148,699High aspect ratio buried power rail metallization202411,804,405Method of forming copper interconnect structure with manganese barrier layer202311,756,786Forming high carbon content flowable dielectric film with low processing damage202311,756,887Backside floating metal for increased capacitance202311,676,854Selective ILD deposition for fully aligned via with airgap202311,621,189Barrier-less prefilled via formation202311,569,134Wafer backside engineering for wafer stress control202311,315,827Skip via connection between metallization levels202211,177,169Interconnects with gouged vias202111,177,162Trapezoidal interconnect at tight BEOL pitch202111,164,815Bottom barrier free interconnects without voids202111,152,257Barrier-less prefilled via formation202111,152,299Hybrid selective dielectric deposition for aligned via integration2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to IBM (25)· patent assignee history
2021–2026Based in US· patent location history
2023Patents assigned to TESSERA LLC (2)· patent assignee history
2025Patents assigned to ADEIA SEMICONDUCTOR SOLUTIONS LLC (1)· patent assignee history
2026Patents assigned to INT BUSINESS MACHINES CORPORATION (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 25 | 2021–2026 |
| TESSERA LLC | 2 | 2023 |
| ADEIA SEMICONDUCTOR SOLUTIONS LLC | 1 | 2025 |
| INT BUSINESS MACHINES CORPORATION | 1 | 2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 29 | 2021–2026 |