Inventor
Yuan-Ju Chao
Inventor
Cupertino, CA, US
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Mprimary
H03MCoding55%
H03GControl of amplification10%
H03KPulse technique10%
G05FSystems for regulating electric or magnetic variables6%
G06FElectric digital data processing3%
G11CStatic stores3%
H01GCapacitors3%
H03FAmplifiers3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
Y10TTechnical subjects covered by former us classification3%
PatentTitleYear
10,873,339On-chip pattern generator for high speed digital-to-analog converter202010,715,163Method of capacitive DAC calibration for SAR ADC202010,686,459Programmable gain amplifier (PGA) embedded pipelined analog to digital converters (ADC) for wide input full scale range202010,644,713Process, voltage and temperature optimized asynchronous SAR ADC202010,523,228Method of capacitive DAC calibration for SAR ADC201910,505,559Process, voltage and temperature optimized asynchronous SAR ADC201910,460,061System and method for anti reverse engineering for analog integrated circuit201910,128,860High speed SAR ADC using comparator output triggered binary-search timing scheme and bit-dependent DAC settling201810,014,874System and method of minimizing differential non-linearity (DNL) for high resolution current steering DAC20189,979,382Programmable duty-cycle low jitter differential clock buffer20189,866,236'Appapatus and method for fast conversion, compact, ultra low power, wide supply range auxiliary digital to analog converters'20189,843,336'System and method of minimizing differential non-linearity (DNL) for high resolution current steering DAC'20179,813,075'Apparatus and method of self-healing data converters'20179,774,337'High speed SAR ADC using comparator output triggered binary-search timing scheme and bit-dependent DAC settling'20179,667,263'Apparatus and method of self-healing data converters'20179,621,180'Apparatus and method for fast conversion, compact, ultra low power, wide supply range auxiliary digital to analog converters'20179,418,788'Precision half cell for sub-FEMTO unit cap and capacitive DAC architecture in SAR ADC'20168,610,612'Tree structured supply and bias distribution layout'20138,537,040'Data converter current sources using thin-oxide core devices'20137,808,322'System and method for modifying output power of an information communication system'20107,733,076'Dual reference current generation using a single external reference resistor'20107,167,045'System and method for modifying output power of an information communication system'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2020Based in Cupertino, CA, US· patent location history
2013–2018Patents assigned to CHAO YUAN-JU (8)· patent assignee history
2013Based in Santa Clara, CA, US· patent location history
2017–2018Patents assigned to CHU TA-SHUN (4)· patent assignee history
2018–2020Patents assigned to IPGREAT INCORPORATED (9)· patent assignee history
2018–2020Patents assigned to CHAO YUAN JU (4)· patent assignee history
2018Patents assigned to CHU TA SHUN (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IPGREAT INCORPORATED | 9 | 2018–2020 |
| CHAO YUAN-JUself | 8 | 2013–2018 |
| CHAO YUAN JUself | 4 | 2018–2020 |
| CHU TA-SHUN | 4 | 2017–2018 |
| CHU TA SHUN | 3 | 2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| Cupertino, California, US | 20 | 2007–2020 |
| Santa Clara, California, US | 2 | 2013 |