Inventor
Bernd Goebel
Inventor
Munich, DE
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices50%
H10DInorganic electric semiconductor devices16%
G11CStatic stores9%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests9%
A01MCatching, trapping or scaring of animals3%
B05BSpraying apparatus3%
B82YSpecific uses or applications of nanostructures3%
H10NElectric solid-state devices not otherwise provided for3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
PatentTitleYear
7,141,845'DRAM cell array and memory cell arrangement having vertical memory cells and methods for fabricating the same'20067,109,544'Architecture for vertical transistor cells and transistor-controlled memory cells'20067,066,402'Spraying device for spraying liquids, in particular, for spraying liquids for agricultural purposes'20067,064,373'Architecture and fabrication method of a vertical memory cell'20066,977,405'Semiconductor memory with memory cells comprising a vertical selection transistor and method for fabricating it'20056,930,325'Test structure for improved vertical memory arrays'20056,853,023'Semiconductor memory cell configuration and a method for producing the configuration'20056,750,095'Integrated circuit with vertical transistors'20046,586,795'DRAM cell configuration whose memory cells can have transistors and capacitors with improved electrical properties'20036,579,729'Memory cell configuration and method for fabricating it'20036,566,202'Integrated circuit having at least two vertical MOS transistors and method for manufacturing same'20036,379,978'Memory cell configuration in which an electrical resistance of a memory element represents an information item and can be influenced by a magnetic field, and method for fabricating it'20026,376,313'Integrated circuit having at least two vertical MOS transistors and method for manufacturing same'20026,352,894'Method of forming DRAM cell arrangement'20026,309,930'SRAM cell arrangement and method for manufacturing same'20016,222,753'SRAM cell arrangement and method for manufacturing same'20016,172,391'DRAM cell arrangement and method for the manufacture thereof'20016,097,049'DRAM cell arrangement'20006,075,265'DRAM cell arrangement and method for its fabrication'20006,044,009'DRAM cell arrangement and method for its production'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2003Patents assigned to SIEMENS AG (9)· patent assignee history
2000–2005Based in Munich, DE· patent location history
2002–2006Patents assigned to INFINEON TECHNOLOGIES AG (10)· patent assignee history
2002Based in Mnchen, DE· patent location history
2003–2006Based in Dresden, DE· patent location history
2006Patents assigned to LECHLER GMBH (1)· patent assignee history
2006Based in Remseck, DE· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INFINEON TECHNOLOGIES AG | 10 | 2002–2006 |
| SIEMENS AG | 9 | 2000–2003 |
| LECHLER GMBH | 1 | 2006 |
Locations
| Location | Patents | Span |
|---|---|---|
| Munich, DE | 10 | 2000–2005 |
| Dresden, DE | 8 | 2003–2006 |
| Remseck, DE | 1 | 2006 |
| Mnchen, DE | 1 | 2002 |