LexDanaLexDanabeta
Inventor

Hai Li

Inventor
Eden Prairie, MN, US

Overview

83→
Patents
2010–2021
Patent span
Physics
Primary field (CPC G)

Patents· 83 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores64%
G06FElectric digital data processing8%
H10BElectronic memory devices5%
H10NElectric solid-state devices not otherwise provided for5%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
G01RMeasuring electric variables3%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%
G06GAnalogue computers2%
G06NComputing arrangements based on specific computational models2%
H04LTransmission of digital information, e.g. telegraphic communication2%
PatentTitleYear
11,044,305Cloud federation as a service202111,032,417Collaborative phone reputation system202111,032,365Ad hoc decentralized cloud infrastructure202110,762,957Two-dimensionally accessible non-volatile memory202010,684,778Data updating in non-volatile memory20209,715,655'Method and apparatus for performing close-loop programming of resistive memory devices in crossbar array based hardware circuits and systems'20179,627,024'Magnetic-assisted nondestructive self-reference sensing method for spin-transfer torque random access memory'20179,455,030'Method and apparatus for performing signal processing on a crossbar array of resistive memory devices'20169,152,827'Apparatus for performing matrix vector multiplication approximation using crossbar arrays of resistive memory devices'20159,128,821'Data updating in non-volatile memory'20158,966,181'Memory hierarchy with non-volatile filter and victim caches'20158,934,281'Bit set modes for a resistive sense memory cell array'20158,675,401'Spin-transfer torque memory self-reference read method'20148,650,355'Non-volatile resistive sense memory on-chip cache'20148,553,454'Predictive thermal preconditioning and timing control for non-volatile memory cells'20138,537,587'Dual stage sensing for non-volatile memory'20138,526,252'Quiescent testing of non-volatile memory array'20138,526,215'Spatial correlation of reference cells in resistive memory array'20138,514,605'MRAM diode array and access method'20138,482,957'Three dimensionally stacked non volatile memory units'20138,446,752'Programmable metallization cell switch and memory units containing the same'20138,416,614'Spin-transfer torque memory non-destructive self-reference read method'20138,416,615'Transmission gate-based spin-transfer torque memory unit'20138,411,495'Spin-transfer torque memory self-reference read method'20138,391,055'Magnetic tunnel junction and memristor apparatus'20138,296,620'Data devices including multiple error correction codes and methods of utilizing'20128,289,746'MRAM diode array and access method'20128,289,786'Data storage using read-mask-write operation'20128,213,216'Shared bit line and source line resistive sense memory structure'20128,213,259'Non-volatile memory cell with resistive sense element block erase and uni-directional write'20128,213,215'Resistive sense memory calibration for self-reference read method'20128,203,862'Voltage reference generation with selectable dummy regions'20128,203,893'Write current compensation using word line boosting circuitry'20128,203,899'Memory cell with proportional current self-reference sensing'20128,199,562'Memory cell with enhanced read and write sense margins'20128,199,563'Transmission gate-based spin-transfer torque memory unit'20128,194,437'Computer memory device with multiple interfaces'20128,154,914'Predictive thermal preconditioning and timing control for non-volatile memory cells'20128,139,397'Spatial correlation of reference cells in resistive memory array'20128,116,122'Spin-transfer torque memory self-reference read method'20128,116,123'Spin-transfer torque memory non-destructive self-reference read method'20128,098,513'Memory array with read reference voltage cells'20128,098,516'Static source plane in STRAM'20128,081,504'Computer memory device with status register'20118,068,359'Static source plane in stram'20118,059,453'Magnetic tunnel junction and memristor apparatus'20118,054,675'Variable write and read methods for resistive random access memory'20118,054,678'Stuck-at defect condition repair for a non-volatile memory cell'20118,054,673'Three dimensionally stacked non volatile memory units'20118,050,072'Dual stage sensing for non-volatile memory'20118,045,412'Multi-stage parallel data transfer'20118,040,713'Bit set modes for a resistive sense memory cell array'20118,040,743'Data storage using read-mask-write operation'20118,009,457'Write current compensation using word line boosting circuitry'20117,974,119'Transmission gate-based spin-transfer torque memory unit'20117,974,121'Write current compensation using word line boosting circuitry'20117,966,581'Generic non-volatile service layer'20117,952,917'Variable write and read methods for resistive random access memory'20117,944,729'Simultaneously writing multiple addressable blocks of user data to a resistive sense memory cell array'20117,944,730'Write method with voltage line tuning'20117,944,731'Resistive sense memory array with partial block update capability'20117,940,548'Shared bit line and source line resistive sense memory structure'20117,936,588'Memory array with read reference voltage cells'20117,936,580'MRAM diode array and access method'20117,936,622'Defective bit scheme for multi-layer integrated memory device'20117,936,625'Pipeline sensing using voltage storage elements to read non-volatile memory cells'20117,916,515'Non-volatile memory read/write verify'20117,916,528'Predictive thermal preconditioning and timing control for non-volatile memory cells'20117,898,838'Resistive sense memory calibration for self-reference read method'20117,898,844'Magnetic tunnel junction and memristor apparatus'20117,894,250'Stuck-at defect condition repair for a non-volatile memory cell'20117,885,097'Non-volatile memory array with resistive sense element block erase and uni-directional write'20117,881,094'Voltage reference generation for resistive sense memory cells'20117,876,599'Spatial correlation of reference cells in resistive memory array'20117,859,891'Static source plane in stram'20107,855,923'Write current compensation using word line boosting circuitry'20107,852,660'Enhancing read and write sense margins in a resistive sense element'20107,852,665'Memory cell with proportional current self-reference sensing'20107,830,700'Resistive sense memory array with partial block update capability'20107,830,726'Data storage using read-mask-write operation'20107,826,255'Variable write and read methods for resistive random access memory'20107,755,923'Memory array with read reference voltage cells'20107,755,965'Temperature dependent system for reading ST-RAM'2010

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2010–2020Patents assigned to SEAGATE TECHNOLOGY LLC (75)· patent assignee history
2010–2020Based in Eden Prairie, MN, US· patent location history
2011–2015Patents assigned to LI HAI (36)· patent assignee history
2011–2015Patents assigned to CHEN YIRAN (31)· patent assignee history
2011–2014Patents assigned to LIU HONGYUE (21)· patent assignee history
2011–2015Patents assigned to LU YONG (12)· patent assignee history
2011Based in Eden Praire, MN, US· patent location history
2015–2017Based in Pittsburg, PA, US· patent location history
2016–2020Based in Pittsburgh, PA, US· patent location history
2021Based in El Dorado Hills, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SEAGATE TECHNOLOGY LLC752010–2020
LI HAIself362011–2015
CHEN YIRAN312011–2015
LIU HONGYUE212011–2014
LU YONG122011–2015
Locations
LocationPatentsSpan
Eden Prairie, Minnesota, US742010–2020
El Dorado Hills, California, US32021
Pittsburgh, Pennsylvania, US32016–2020
Pittsburg, Pennsylvania, US22015–2017
Eden Praire, Minnesota, US12011