Inventor
Mary D. Brown
Inventor
Austin, TX, US
Overview
Patents· 26 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing90%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use10%
PatentTitleYear
10,296,339Thread transition management201910,275,251Processor for avoiding reduced performance using instruction metadata to determine not to maintain a mapping of a logical register to a physical register in a first level register file201910,055,226Thread transition management201810,007,616Methods for core recovery after a cold start20189,959,121Bypassing a higher level register file in a processor having a multi-level register file and a set of bypass registers20189,703,561'Thread transition management'20179,286,068'Efficient usage of a multi-level register file utilizing a register file bypass'20168,725,993'Thread transition management'20148,661,228'Multi-level register file supporting multiple threads'20148,661,227'Multi-level register file supporting multiple threads'20148,631,223'Register file supporting transactional processing'20148,489,863'Processor including age tracking of issue queue instructions'20138,380,964'Processor including age tracking of issue queue instructions'20138,239,661'System and method for double-issue instructions using a dependency matrix'20128,135,942'System and method for double-issue instructions using a dependency matrix and a side issue queue'20128,127,116'Dependency matrix with reduced area and power consumption'20128,108,655'Selecting fixed-point instructions to issue on load-store unit'20128,103,852'Information handling system including a processor with a bifurcated issue queue'20128,099,582'Tracking deallocated load instructions using a dependence matrix'20128,086,826'Dependency tracking for enabling successive processor instructions to issue'20118,078,999'Structure for implementing speculative clock gating of digital logic circuits'20118,037,366'Issuing instructions in-order in an out-of-order processor using false dependencies'20117,991,979'Issuing load-dependent instructions in an issue queue in a processing unit of a data processing system'20117,971,161'Apparatus and method for implementing speculative clock gating of digital logic circuits'20117,689,812'Method and system for restoring register mapper states for an out-of-order microprocessor'20106,988,185'Select-free dynamic instruction scheduling'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2019Based in Austin, TX, US· patent location history
2010–2019Patents assigned to IBM (24)· patent assignee history
2011–2014Patents assigned to BROWN MARY D (9)· patent assignee history
2011–2013Patents assigned to BROWN MARY DOUGLASS (5)· patent assignee history
2012–2014Patents assigned to ABERNATHY CHRISTOPHER M (7)· patent assignee history
2012–2013Patents assigned to BISHOP JAMES WILSON (4)· patent assignee history
2012Based in Ausin, TX, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 24 | 2010–2019 |
| BROWN MARY Dself | 9 | 2011–2014 |
| ABERNATHY CHRISTOPHER M | 7 | 2012–2014 |
| BROWN MARY DOUGLASSself | 5 | 2011–2013 |
| BISHOP JAMES WILSON | 4 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 24 | 2006–2019 |
| Ausin, Texas, US | 2 | 2012 |