Inventor
Derrick C. Lin
Inventor
Foster City, CA, US
Overview
Patents· 48 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing85%
H04LTransmission of digital information, e.g. telegraphic communication7%
G06TImage data processing or generation, in general2%
H04WWireless communication networks2%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications2%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%
PatentTitleYear
9,820,229'Dynamic voltage and frequency scaling in wireless modems'20177,996,670'Classification engine in a cryptography acceleration chip'20117,600,131'Distributed processing in a cryptography acceleration chip'20097,480,686'Method and apparatus for executing packed shift operations'20097,461,109'Method and apparatus for providing packed shift operations in a processor'20087,451,169'Method and apparatus for providing packed shift operations in a processor'20087,380,278'Protecting software environment in isolated execution'20087,254,707'Platform and method for remote attestation of a platform'20077,194,634'Attestation key memory device and bus'20077,117,232'Method and apparatus for providing packed shift operations in a processor'20067,111,176'Generating isolated bus cycles for isolated execution'20067,096,497'File checking using remote signing authority via a network'20067,089,418'Managing accesses in a processor for isolated execution'20067,085,935'Managing a secure environment using a chipset in isolated execution mode'20067,082,615'Protecting software environment in isolated execution'20067,073,071'Platform and method for generating and utilizing a protected audit log'20067,013,481'Attestation key memory device and bus'20067,013,484'Managing a secure environment using a chipset in isolated execution mode'20066,996,710'Platform and method for issuing and certifying a hardware-protected attestation key'20066,990,579'Platform and method for remote attestation of a platform'20066,957,332'Managing a secure platform using a hierarchical executive architecture in isolated execution mode'20056,941,458'Managing a secure platform using a hierarchical executive architecture in isolated execution mode'20056,934,817'Controlling access to multiple memory zones in an isolated execution environment'20056,901,420'Method and apparatus for performing packed shift operations'20056,795,905'Controlling accesses to isolated memory using a memory controller for isolated execution'20046,769,058'Resetting a processor in an isolated execution environment'20046,760,441'Generating a key hieararchy for use in an isolated execution environment'20046,754,815'Method and system for scrubbing an isolated area of memory after reset of a processor operating in isolated execution mode if a cleanup flag is set'20046,738,793'Processor capable of executing packed shift operations'20046,678,825'Controlling access to multiple isolated memories in an isolated execution environment'20046,633,963'Controlling access to multiple memory zones in an isolated execution environment'20036,631,452'Register stack engine having speculative load/store modes'20036,631,389'Apparatus for performing packed shift operations'20036,507,904'Executing isolated mode instructions in a secure system running in privilege rings'20036,275,834'Apparatus for performing packed shift operations'20016,205,542'Processor pipeline including replay'20016,076,153'Processor pipeline including partial replay'20006,035,316'Apparatus for performing multiply-add operations on packed data'20006,035,389'Scheduling instructions with different latencies'20005,991,884'Method for reducing peak power in dispatching instructions to multiple execution units'19995,974,525'System for allowing multiple instructions to use the same logical registers by remapping them to separate physical segment registers when the first is being utilized'19995,959,636'Method and apparatus for performing saturation instructions using saturation limit values'19995,959,874'Method and apparatus for inserting control digits into packed data to perform packed arithmetic operations'19995,881,279'Method and apparatus for handling invalid opcode faults via execution of an event-signaling micro-operation'19995,852,726'Method and apparatus for executing two types of instructions that specify registers of a shared logical register file in a stack and a non-stack referenced manner'19985,835,782'Packed/add and packed subtract operations'19985,835,748'Method for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file'19985,701,508'Executing different instructions that cause different data type operations to be performed on single logical register file'1997Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1997–2009Patents assigned to INTEL CORP (44)· patent assignee history
1997–2009Based in Foster City, CA, US· patent location history
2003Patents assigned to IDEA CORP (1)· patent assignee history
2003–2011Based in San Mateo, CA, US· patent location history
2009–2011Patents assigned to BROADCOM CORP (2)· patent assignee history
2017Patents assigned to QUALCOMM INC (1)· patent assignee history
2017Based in Belmont, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 44 | 1997–2009 |
| BROADCOM CORP | 2 | 2009–2011 |
| IDEA CORP | 1 | 2003 |
| QUALCOMM INC | 1 | 2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Foster City, California, US | 30 | 1997–2009 |
| San Mateo, California, US | 17 | 2003–2011 |
| Belmont, California, US | 1 | 2017 |