Inventor

Fred D. Fishburn

Inventor

Boise, ID, US

Overview

1993–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 71 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices24%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1019%

H10BElectronic memory devices17%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests8%

H01GCapacitors3%

H01LSemiconductor devices3%

H05KPrinted circuits3%

Y10TTechnical subjects covered by former us classification3%

C23CCoating metallic material2%

PatentTitleYear

10,685,785Apparatuses, multi-chip modules and capacitive chips2020 10,607,995Memory arrays2020 10,483,043Apparatuses, multi-chip modules and capacitive chips2019 10,418,182Apparatuses, multi-chip modules and capacitive chips2019 10,236,127Apparatuses, multi-chip modules and capacitive chips2019 10,014,115Apparatuses, multi-chip modules and capacitive chips2018 9,767,962'Apparatuses, multi-chip modules and capacitive chips'2017 8,687,426'Multi-semiconductor material vertical memory strings, strings of memory cells having individually biasable channel regions, memory arrays incorporating such strings, and methods of accesssing and forming the same'2014 8,580,666'Methods of forming conductive contacts'2013 8,395,941'Multi-semiconductor material vertical memory strings, strings of memory cells having individually biasable channel regions, memory arrays incorporating such strings, and methods of accessing and forming the same'2013 8,273,619'Methods of implanting dopant into channel regions'2012 8,232,206'Methods of forming electrical contacts to structures that are at different heights over a substrate relative to one another'2012 8,163,613'Methods of forming a plurality of capacitors'2012 8,026,542'Low resistance peripheral local interconnect contacts with selective wet strip of titanium'2011 7,935,602'Semiconductor processing methods'2011 7,767,514'Methods of implanting dopant into channel regions'2010 7,759,193'Methods of forming a plurality of capacitors'2010 7,713,817'Methods of forming semiconductor structures'2010 7,674,670'Methods of forming threshold voltage implant regions'2010 7,659,161'Methods of forming storage nodes for a DRAM array'2010 7,638,392'Methods of forming capacitor structures'2009 7,605,033'Low resistance peripheral local interconnect contacts with selective wet strip of titanium'2009 7,569,453'Contact structure'2009 7,538,036'Methods of forming openings, and methods of forming container capacitors'2009 7,517,754'Methods of forming semiconductor constructions'2009 7,473,644'Method for forming controlled geometry hardmasks including subresolution elements'2009 7,445,990'Methods of forming a plurality of capacitors'2008 7,442,600'Methods of forming threshold voltage implant regions'2008 7,440,255'Capacitor constructions and methods of forming'2008 7,413,952'Methods of forming a plurality of circuit components and methods of forming a plurality of structures suspended elevationally above a substrate'2008 7,384,847'Methods of forming DRAM arrays'2008 7,368,372'Methods of fabricating multiple sets of field effect transistors'2008 7,341,909'Methods of forming semiconductor constructions'2008 7,335,935'Semiconductor structures'2008 7,329,618'Ion implanting methods'2008 7,329,607'Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby'2008 7,321,149'Capacitor structures, and DRAM arrays'2008 7,321,150'Semiconductor device precursor structures to a double-sided capacitor or a contact'2008 7,288,806'DRAM arrays'2007 7,279,379'Methods of forming memory arrays; and methods of forming contacts to bitlines'2007 7,273,779'Method of forming a double-sided capacitor'2007 7,271,086'Microfeature workpieces and methods of forming a redistribution layer on microfeature workpieces'2007 7,268,039'Method of forming a contact using a sacrificial structure'2007 7,220,663'Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby'2007 7,205,227'Methods of forming CMOS constructions'2007 7,202,127'Methods of forming a plurality of capacitors'2007 7,186,642'Low temperature nitride used as Cu barrier layer'2007 7,176,576'Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby'2007 7,157,324'Transistor structure having reduced transistor leakage attributes'2007 7,153,778'Methods of forming openings, and methods of forming container capacitors'2006 7,135,401'Methods of forming electrical connections for semiconductor constructions'2006 7,107,777'MEMS heat pumps for integrated circuit heat dissipation'2006 7,105,899'Transistor structure having reduced transistor leakage attributes'2006 7,084,004'MEMS heat pumps for integrated circuit heat dissipation'2006 7,071,055'Method of forming a contact structure including a vertical barrier structure and two barrier layers'2006 7,067,378'Methods of fabricating multiple sets of field effect transistors'2006 7,060,569'Methods of fabricating multiple sets of field effect transistors'2006 7,060,570'Methods of fabricating multiple sets of field effect transistors'2006 7,005,379'Semiconductor processing methods for forming electrical contacts'2006 6,984,893'Low temperature nitride used as Cu barrier layer'2006 6,962,846'Methods of forming a double-sided capacitor or a contact using a sacrificial structure'2005 6,927,135'Methods of fabricating multiple sets of field effect transistors'2005 6,787,833'Integrated circuit having a barrier structure'2004 6,756,678'Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby'2004 6,707,088'Method of forming integrated circuitry, method of forming a capacitor, method of forming DRAM integrated circuitry and DRAM integrated category'2004 6,613,671'Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby'2003 6,492,267'Low temperature nitride used as Cu barrier layer'2002 6,475,855'Method of forming integrated circuitry, method of forming a capacitor and method of forming DRAM integrated circuitry'2002 6,372,574'Method of forming a capacitor container electrode and method of patterning a metal layer by selectively silicizing the electrode or metal layer and removing the silicized portion'2002 5,972,796'In-situ barc and nitride etch process'1999 5,252,506'Method to eliminate gate filaments on field plate isolated devices'1993

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1993–1999Patents assigned to TEXAS INSTRUMENTS INC (2)· patent assignee history

1993–1999Based in Richardson, TX, US· patent location history

2002–2020Patents assigned to MICRON TECHNOLOGY INC (68)· patent assignee history

2002–2013Based in Boise, ID, US· patent location history

2007–2013Based in Woodbridge, VA, US· patent location history

2010–2012Based in Manassas, VA, US· patent location history

2012Patents assigned to FISHBURN FRED D (3)· patent assignee history

2012Patents assigned to BEIGEL KURT D (1)· patent assignee history

2013Patents assigned to FISHBURN FRED (2)· patent assignee history

2017–2020Based in Aptos, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MICRON TECHNOLOGY INC	68	2002–2020
FISHBURN FRED Dself	3	2012
FISHBURN FREDself	2	2013
TEXAS INSTRUMENTS INC	2	1993–1999
BEIGEL KURT D	1	2012

Locations

Location	Patents	Span
Boise, ID, US	56	2002–2013
Aptos, California, US	6	2017–2020
Woodbridge, Virginia, US	3	2007–2013
Manassas, Virginia, US	2	2010–2012
Richardson, Texas, US	2	1993–1999