Inventor
GUAN-LIN CHEN
Inventor
TW
Overview
Patents· 71 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices30%
H01LSemiconductor devices26%
B82YSpecific uses or applications of nanostructures25%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%
H01RElectrically-conductive connections1%
G11CStatic stores0%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems0%
H10BElectronic memory devices0%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications0%
PatentTitleYear
12,598,787Field effect transistor with dual layer isolation structure and method202612,557,376Semiconductor device structure and methods of forming the same202612,538,569Tuning tensile strain on FinFET202612,520,565Semiconductor structure and method for forming the same202612,507,440Multi-layer channel structures and methods of fabricating the same in field-effect transistors202512,464,812Semiconductor device structure including forksheet transistors and methods of forming the same202512,464,750Semiconductor device and formation method thereof202512,453,147Semiconductor structure and method of fabricating the semiconductor structure202512,446,305Uniform gate width for nanostructure devices202512,414,357Self-aligned metal gate for multigate device202512,402,407Gap-insulated semiconductor device202512,389,643Semiconductor device structure202512,376,343Self-aligned spacers for multi-gate devices and method of fabrication thereof202512,376,365Nanosheet devices with hybrid structures and methods of fabricating the same202512,369,369Field effect transistor with asymmetrical source/drain region and method202512,347,486Forming method of resistive random-access memory array202512,327,963Electrical receptacle connector with central shield202512,322,907Electrical receptacle connector with metallic plate202512,324,229Semiconductor device structure including forksheet transistors and methods of forming the same202512,302,630Integrated circuit with backside trench for metal gate definition202512,300,719Structure and formation method of semiconductor device with isolation structure202512,300,723Transistor including downward extending silicide202512,300,731Multigate device with air gap spacer and backside rail contact and method of fabricating thereof202512,266,704Semiconductor devices including horizontal gate-all-around (hGAA) nanostructure transistors and methods of forming202512,249,621Semiconductor structure with dielectric fin feature202512,230,928Electrical receptacle connector202512,191,305Integration of silicon channel nanostructures and silicon-germanium channel nanostructures202512,183,799Semiconductor device with gate isolation features and fabrication method of the same202412,170,334Isolation structures and methods of forming the same in field-effect transistors202412,170,279Hybrid semiconductor device202412,148,812Nano-sheet-based devices having inner spacer structures or gate portions with variable dimensions202412,132,115Semiconductor device structure with dielectric stressor202412,125,877Nanostructure field-effect transistor device with dielectric layer for reducing substrate leakage or well isolation leakage and methods of forming202412,107,087Semiconductor device with gate isolation structure and method for forming the same202412,100,770Field effect transistor with gate isolation structure and method202412,057,477Semiconductor structure with hybrid nanostructures202412,040,371Multi-layer channel structures and methods of fabricating the same in field-effect transistors preliminary class202412,033,899Self-aligned metal gate for multigate device202412,009,261Nanosheet devices with hybrid structures and methods of fabricating the same202411,996,410Gap-insulated semiconductor device202411,990,471Gate isolation for multigate device202411,984,488Multigate device with air gap spacer and backside rail contact and method of fabricating thereof202411,942,478Semiconductor device structure and methods of forming the same202411,942,513Semiconductor structure and method of fabricating the semiconductor structure202411,876,119Semiconductor device with gate isolation features and fabrication method of the same202411,862,734Self-aligned spacers for multi-gate devices and method of fabrication thereof202411,855,138Semiconductor device structure202311,855,078Semiconductor device structure including forksheet transistors and methods of forming the same202311,855,079Integrated circuit with backside trench for metal gate definition202311,855,096Uniform gate width for nanostructure devices202311,817,504Isolation structures and methods of forming the same in field-effect transistors202311,798,944Integration of silicon channel nanostructures and silicon-germanium channel nanostructures202311,710,737Hybrid semiconductor device202311,699,729Semiconductor devices and methods202311,682,697Fin recess last process for FinFET fabrication202311,670,550Nanostructure field-effect transistor device and method of forming202311,637,042Self-aligned metal gate for multigate device202311,637,102Gate isolation for multigate device202311,631,770Structure and formation method of semiconductor device with stressor202311,610,977Methods of forming nano-sheet-based devices having inner spacer structures with different widths202311,581,415Multi-layer channel structures and methods of fabricating the same in field-effect transistors202311,552,574Interleaved three phase Y-delta connected power converter202311,527,534Gap-insulated semiconductor device202211,462,612Semiconductor device structure202211,315,925Uniform gate width for nanostructure devices202211,302,825Self-aligned spacers for multi-gate devices and method of fabrication thereof202211,296,199Semiconductor devices and methods202211,296,081Integration of silicon channel nanostructures and silicon-germanium channel nanostructures202211,257,903Method for manufacturing semiconductor structure with hybrid nanostructures202211,222,948Semiconductor structure and method of fabricating the semiconductor structure202211,201,225Structure and formation method of semiconductor device with stressor2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (66)· patent assignee history
2021–2026Based in TW· patent location history
2023Patents assigned to UNIV NAT TAIWAN SCIENCE & TECHNOLOGY (1)· patent assignee history
2025Patents assigned to ADVANCED CONNECTEK INC (3)· patent assignee history
2025Patents assigned to UNITED MICROELECTRONICS CORP (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 66 | 2021–2026 |
| ADVANCED CONNECTEK INC | 3 | 2025 |
| UNITED MICROELECTRONICS CORP | 1 | 2025 |
| UNIV NAT TAIWAN SCIENCE & TECHNOLOGY | 1 | 2023 |
Locations
| Location | Patents | Span |
|---|---|---|
| TW | 71 | 2021–2026 |