Inventor
Takafumi Kunihiro
Inventor
Boise, ID, US
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores42%
H01LSemiconductor devices21%
H10BElectronic memory devices15%
H10NElectric solid-state devices not otherwise provided for13%
G06FElectric digital data processing4%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use4%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
PatentTitleYear
10,783,961Memory cells, memory systems, and memory programming methods202010,622,067Memory systems and memory writing methods202010,438,675Memory programming methods and memory systems201910,438,661Memory devices and methods of writing memory cells at different moments in time201910,395,731Memory cells, memory systems, and memory programming methods201910,249,366Integrated circuit system with non-volatile memory stress suppression and method of manufacture thereof20199,911,489'Memory cells, memory systems, and memory programming methods'20189,905,300'Memory device with variable trim parameters'20189,691,441'Memory programming methods and memory systems'20179,646,690'Non-volatile memory system with reset verification mechanism and method of operation thereof'20179,594,516'Memory device with variable trim parameters'20179,530,469'Integrated circuit system with non-volatile memory stress suppression and method of manufacture thereof'20169,349,450'Memory devices and memory operational methods including single erase operation of conductive bridge memory cells'20169,293,196'Memory cells, memory systems, and memory programming methods'20169,153,317'Non-volatile memory system with power reduction mechanism and method of operation thereof'20159,135,978'Memory programming methods and memory systems'20159,093,147'Method and apparatus for common source line charge transfer'20159,070,441'Non-volatile memory system with reset verification mechanism and method of operation thereof'20159,007,837'Non-volatile memory system with reset control mechanism and method of operation thereof'20158,953,404'Semiconductor device having an electrical fuse element'2015Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2015–2020Patents assigned to MICRON TECHNOLOGY INC (10)· patent assignee history
2015–2017Patents assigned to SONY CORP (8)· patent assignee history
2015Patents assigned to KUNIHIRO TAKAFUMI (2)· patent assignee history
2015Patents assigned to AMARI KOICHI (1)· patent assignee history
2015–2020Based in Boise, ID, US· patent location history
2015–2019Based in Tokyo, JP· patent location history
2015Based in Kanagawa, JP· patent location history
2016–2019Patents assigned to SONY SEMICONDUCTOR SOLUTIONS CORP (5)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 10 | 2015–2020 |
| SONY CORP | 8 | 2015–2017 |
| SONY SEMICONDUCTOR SOLUTIONS CORP | 5 | 2016–2019 |
| KUNIHIRO TAKAFUMIself | 2 | 2015 |
| AMARI KOICHI | 1 | 2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Boise, ID, US | 13 | 2015–2020 |
| Tokyo, JP | 6 | 2015–2019 |
| Kanagawa, JP | 1 | 2015 |