Inventor
Yoichi Koyanagi
Inventor
Kawasaki, JP
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H04Lprimary
H04LTransmission of digital information, e.g. telegraphic communication32%
G06FElectric digital data processing26%
H03KPulse technique10%
H04BTransmission10%
H03MCoding6%
H04JMultiplex communication6%
G06NComputing arrangements based on specific computational models3%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes3%
G11CStatic stores3%
PatentTitleYear
11,132,422Automating solving NP problems in annealer systems20219,813,188'Transmitting circuit, communication system, and communication method'20179,684,332'Timing control circuit'20179,160,380'Transmission circuit, communication system and transmission method'20159,049,059'Receiving circuit'20158,836,369'Latch circuit, flip-flop circuit, and divider'20148,750,430'Data receiver circuit'20148,593,313'Parallel-to-serial conversion circuit, information processing apparatus, information processing system, and parallel-to-serial conversion method'20138,102,288'Data transmitting circuit and method'20127,561,616'System and method for equalizing high-speed data transmission'20097,512,178'Equalizing a signal for transmission'20097,427,878'Low-voltage differential signal driver for high-speed digital transmission'20087,173,965'Equalizing a signal for transmission'20077,065,135'System and method for equalizing high-speed data transmission'20066,898,742'System and method for automatic deskew across a high speed, parallel interconnection'20056,636,993'System and method for automatic deskew across a high speed, parallel interconnection'20036,493,320'Automatic initialization and tuning across a high speed, plesiochronous, parallel link'20026,115,803'Parallel computer which verifies direct data transmission between local memories with a send complete flag'20005,892,979'Queue control apparatus including memory to save data received when capacity of queue is less than a predetermined threshold'19995,818,755'Storage apparatus having a nonvolatile storage device capable of retaining data after an incomplete write operation and method of accessing same'19985,742,843'Control system for access between processing elements in a parallel computer'19985,604,913'Vector processor having a mask register used for performing nested conditional instructions'1997Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1997–2021Patents assigned to FUJITSU LTD (22)· patent assignee history
1997–2014Based in Kawasaki, JP· patent location history
2002–2009Based in Cupertino, CA, US· patent location history
2008Based in Saratoga, CA, US· patent location history
2012–2014Patents assigned to KOYANAGI YOICHI (3)· patent assignee history
2013–2017Based in Yokohama, JP· patent location history
2021Based in Sunnyvale, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| FUJITSU LTD | 22 | 1997–2021 |
| KOYANAGI YOICHIself | 3 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Kawasaki, JP | 7 | 1997–2014 |
| Cupertino, California, US | 7 | 2002–2009 |
| Yokohama, JP | 6 | 2013–2017 |
| Sunnyvale, California, US | 1 | 2021 |
| Saratoga, California, US | 1 | 2008 |