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Inventor

Alan Holesovsky

Inventor
Loveland, CO, US

Overview

2→
Patents
2006–2009
Patent span
Physics
Primary field (CPC G)

Patents· 2 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing100%
PatentTitleYear
7,480,878'Method and system for layout versus schematic validation of integrated circuit designs'20097,149,989'Method of early physical design validation and identification of texted metal short circuits in an integrated circuit design'2006

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2006Patents assigned to LSI LOGIC CORP (1)· patent assignee history
2006–2009Based in Loveland, CO, US· patent location history
2009Patents assigned to LSI LOGIC CORPORTION (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
LSI LOGIC CORP12006
LSI LOGIC CORPORTION12009
Locations
LocationPatentsSpan
Loveland, CO, US22006–2009