Inventor
Enrique Musoll
Inventor
San Jose, CA, US
Overview
Patents· 37 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing51%
H04LTransmission of digital information, e.g. telegraphic communication43%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
PatentTitleYear
11,093,415Packet processing system, method and device utilizing a port client chain202110,616,144Packet processing system, method and device having reduced static power consumption202010,289,575Packet processing system, method and device utilizing a port client chain201910,061,513Packet processing system, method and device utilizing memory sharing201810,003,551Packet memory system, method and device for preventing underrun20189,747,226'Packet processing system, method and device to optimize packet buffer space'20179,652,171'Datapath subsystem, method and device utilizing memory sharing'20179,612,950'Control path subsystem, method and device utilizing memory sharing'20179,606,942'Packet processing system, method and device utilizing a port client chain'20179,582,215'Packet processing system, method and device utilizing memory sharing'20178,081,645'Context sharing between a streaming processing unit (SPU) and a packet management unit (PMU) in a packet processing environment'20118,077,734'Method and apparatus for predicting characteristics of incoming data packets to enable speculative processing to reduce processor latency'20117,877,481'Method and apparatus for overflowing data packets to a software-controlled memory when they do not fit into a hardware-controlled memory'20117,765,554'Context selection and activation mechanism for activating one of a group of inactive contexts in a processor core for servicing interrupts'20107,707,391'Methods and apparatus for improving fetching and dispatch of instructions in multithreaded processors'20107,649,901'Method and apparatus for optimizing selection of available contexts for packet processing in multi-stream packet processing'20107,644,307'Functional validation of a packet management unit'20107,636,836'Fetch and dispatch disassociation apparatus for multistreaming processors'20097,634,622'Packet processor that generates packet-start offsets to immediately store incoming streamed packets using parallel, staggered round-robin arbitration to interleaved banks of memory'20097,571,270'Monitoring of shared-resource locks in a multi-processor system with locked-resource bits packed into registers to detect starved threads'20097,529,907'Method and apparatus for improved computer load and store operations'20097,415,531'Method and apparatus for predicting characteristics of incoming data packets to enable speculative processing to reduce processor latency'20087,406,586'Fetch and dispatch disassociation apparatus for multi-streaming processors'20087,360,217'Multi-threaded packet processing engine for stateful packet processing'20087,280,548'Method and apparatus for non-speculative pre-fetch operation in data packet processing'20077,197,043'Method for allocating memory space for limited packet head and/or tail growth'20077,165,257'Context selection and activation mechanism for activating one of a group of inactive contexts in a processor core for servicing interrupts'20077,155,516'Method and apparatus for overflowing data packets to a software-controlled memory when they do not fit into a hardware-controlled memory'20067,139,901'Extended instruction set for packet processing applications'20067,139,898'Fetch and dispatch disassociation apparatus for multistreaming processors'20067,082,552'Functional validation of a packet management unit'20067,076,630'Method and apparatus for allocating and de-allocating consecutive blocks of memory in background memo management'20067,065,096'Method for allocating memory space for limited packet head and/or tail growth'20067,058,065'Method and apparatus for preventing undesirable packet download with pending read/write operations in data packet processing'20067,042,887'Method and apparatus for non-speculative pre-fetch operation in data packet processing'20067,035,998'Clustering stream and/or instruction queues for multi-streaming processors'20066,282,614'Apparatus and method for reducing the power consumption of a microprocessor with multiple levels of caches'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001Based in Los Gatos, CA, US· patent location history
2006–2011Patents assigned to MIPS TECH INC (23)· patent assignee history
2006–2021Based in San Jose, CA, US· patent location history
2008–2009Patents assigned to CONSENTRY NETWORKS INC (3)· patent assignee history
2011Patents assigned to MUSOLL ENRIQUE (2)· patent assignee history
2017–2020Patents assigned to CAVIUM INC (9)· patent assignee history
2019–2020Patents assigned to CAVIUM LLC (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MIPS TECH INC | 23 | 2006–2011 |
| CAVIUM INC | 9 | 2017–2020 |
| CONSENTRY NETWORKS INC | 3 | 2008–2009 |
| CAVIUM LLC | 2 | 2019–2020 |
| MUSOLL ENRIQUEself | 2 | 2011 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 36 | 2006–2021 |
| Los Gatos, California, US | 1 | 2001 |