Inventor
David Lepejian
Inventor
Palo Alto, CA, US
Overview
Patents· 4 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores33%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1033%
G01RMeasuring electric variables17%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices17%
PatentTitleYear
6,745,370'Method for selecting an optimal level of redundancy in the design of memories'20046,330,696'Self-testing of DRAMs for multiple faults'20016,154,714'Method for using wafer navigation to reduce testing times of integrated circuit wafers'20006,096,093'Method for using inspection data for improving throughput of stepper operations in manufacturing of integrated circuits'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000Patents assigned to HEURISTIC PHYSICS LAB (2)· patent assignee history
2000–2004Based in Palo Alto, CA, US· patent location history
2001Patents assigned to AGERE SYST GUARDIAN CORP (1)· patent assignee history
2001Based in Milpitas, CA, US· patent location history
2004Patents assigned to HEURISTICS PHYSICS LAB INC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| HEURISTIC PHYSICS LAB | 2 | 2000 |
| AGERE SYST GUARDIAN CORP | 1 | 2001 |
| HEURISTICS PHYSICS LAB INC | 1 | 2004 |
Locations
| Location | Patents | Span |
|---|---|---|
| Palo Alto, California, US | 3 | 2000–2004 |
| Milpitas, California, US | 1 | 2001 |