Inventor

James W. Adkisson

Inventor

Jericho, VT, US

Overview

1984–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 164 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices21%

H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation16%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%

H01LSemiconductor devices9%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h109%

G06FElectric digital data processing6%

H03HImpedance networks, e.g. resonant circuits5%

Y10TTechnical subjects covered by former us classification4%

H10BElectronic memory devices3%

H04NPictorial communication, e.g. television2%

PatentTitleYear

10,818,772Heterojunction bipolar transistors with an inverted crystalline boundary in the base layer2020 10,580,689Contact module for optimizing emitter and contact resistance2020 10,559,743Backside integration of RF filters for RF front end modules and design structure2020 10,331,844Methods of tuning current ratio in a current mirror for transistors formed with the same FEOL layout and a modified BEOL layout2019 10,312,356Heterojunction bipolar transistors with multiple emitter fingers and undercut extrinsic base regions2019 10,277,188Switchable filters and design structures2019 10,217,852Heterojunction bipolar transistors with a controlled undercut formed beneath the extrinsic base2019 10,164,596Switchable filters and design structures2018 10,164,597Switchable filters and design structures2018 10,020,789Switchable filters and design structures2018 9,935,600Switchable filters and design structures2018 9,892,958'Contact module for optimizing emitter and contact resistance'2018 9,843,303'Switchable filters and design structures'2017 9,786,835'Backside integration of RF filters for RF front end modules and design structure'2017 9,608,096'Implementing stress in a bipolar junction transistor'2017 9,607,929'Tsv wafer with improved fracture strength'2017 9,478,615'Blanket short channel roll-up implant with non-angled long channel compensating implant through patterned opening'2016 9,425,269'Replacement emitter for reduced contact resistance'2016 9,343,589'Field effect transistor (FET) with self-aligned double gates on bulk silicon substrate, methods of forming, and related design structures'2016 9,312,370'Bipolar transistor with extrinsic base region and methods of fabrication'2016 9,312,205'Methods of forming a TSV wafer with improved fracture strength'2016 9,300,272'Tunable filter structures and design structures'2016 9,252,733'Switchable filters and design structures'2016 9,252,204'Metal insulator metal (MIM) capacitor structure'2016 9,240,448'Bipolar junction transistors with reduced base-collector junction capacitance'2016 9,225,311'Method of manufacturing switchable filters'2015 9,202,900'Method to bridge extrinsic and intrinsic base by selective epitaxy in BiCMOS technology'2015 9,106,854'Pixel sensor cell with hold node for leakage cancellation and methods of manufacture and design structure'2015 9,099,982'Method of manufacturing switching filters and design structures'2015 9,093,491'Bipolar junction transistors with reduced base-collector junction capacitance'2015 9,058,455'Backside integration of RF filters for RF front end modules and design structure'2015 9,054,671'Tunable filter structures and design structures'2015 9,048,809'Method of manufacturing switchable filters'2015 9,029,229'Semiconductor device and method of forming the device by forming monocrystalline semiconductor layers on a dielectric layer over isolation regions'2015 8,957,405'Graphene field effect transistor'2015 8,927,379'Method to bridge extrinsic and intrinsic base by selective epitaxy in BiCMOS technology'2015 8,910,355'Method of manufacturing a film bulk acoustic resonator with a loading element'2014 8,900,954'Blanket short channel roll-up implant with non-angled long channel compensating implant through patterned opening'2014 8,836,835'Pixel sensor cell with hold node for leakage cancellation and methods of manufacture and design structure'2014 8,796,149'Collector-up bipolar junction transistors in BiCMOS technology'2014 8,786,051'Transistor having a monocrystalline center section and a polycrystalline outer section, and narrow in-substrate collector region for reduced base-collector junction capacitance'2014 8,742,560'Anti-reflection structures for CMOS image sensors'2014 8,743,247'Low lag transfer gate device'2014 8,723,392'Saw filter having planar barrier layer and method of making'2014 8,716,771'Anti-reflection structures for CMOS image sensors'2014 8,673,683'Graphene field effect transistor'2014 8,647,913'Image sensor, method and design structure including non-planar reflector'2014 8,633,055'Graphene field effect transistor'2014 8,610,174'Bipolar transistor with a raised collector pedestal for reduced capacitance'2013 8,546,230'Bipolar transistor with a collector having a protected outer edge portion for reduced based-collector junction capacitance and a method of forming the transistor'2013 8,492,272'Passivated through wafer vias in low-doped semiconductor substrates'2013 8,440,490'CMOS imager photodiode with enhanced capacitance'2013 8,409,904'Methods for forming anti-reflection structures for CMOS image sensors'2013 8,298,853'CMOS pixel sensor cells with poly spacer transfer gates and methods of manufacture'2012 8,299,554'Image sensor, method and design structure including non-planar reflector'2012 8,232,651'Bond pad for wafer and package for CMOS imager'2012 8,232,612'Semiconductor transistors having high-K gate dielectric layers, metal gate electrode regions, and low fringing capacitances'2012 8,227,844'Low lag transfer gate device'2012 8,227,874'Semiconductor transistors having high-K gate dielectric layers and metal gate electrodes'2012 8,168,474'Self-dicing chips using through silicon vias'2012 8,158,453'Methods of forming silicide strapping in imager transfer gate device'2012 8,138,531'Structures, design structures and methods of fabricating global shutter pixel sensor cells'2012 8,138,534'Anti-reflection structures for CMOS image sensors'2012 8,119,456'Bond pad for wafer and package for CMOS imager'2012 8,106,432'CMOS imager photodiode with enhanced capacitance'2012 8,105,861'CMOS image sensor with reduced dark current'2012 8,039,875'Structure for pixel sensor cell that collects electrons and holes'2011 8,034,699'Isolation with offset deep well implants'2011 8,023,021'High efficiency CMOS image sensor pixel employing dynamic voltage supply'2011 8,009,215'Pixel sensor cell with frame storage capability'2011 8,009,216'Pixel sensor cell with frame storage capability'2011 8,003,425'Methods for forming anti-reflection structures for CMOS image sensors'2011 7,977,711'Pixel sensor cell for collecting electrons and holes'2011 7,964,967'High surface area aluminum bond pad for through-wafer connections to an electronic package'2011 7,943,997'Fully-depleted low-body doping field effect transistor (FET) with reverse short channel effects (SCE) induced by self-aligned edge back-gate(s)'2011 7,935,604'Method of making small geometry features'2011 7,923,750'Pixel sensor cell, methods and design structure including optically transparent gate'2011 7,915,571'On demand circuit function execution employing optical sensing'2011 7,886,240'Modifying layout of IC based on function of interconnect and related circuit and design structure'2011 7,829,945'Lateral diffusion field effect transistor with asymmetric gate dielectric profile'2010 7,824,961'Stacked imager package'2010 7,800,147'CMOS image sensor with reduced dark current'2010 7,790,559'Semiconductor transistors having high-K gate dielectric layers and metal gate electrodes'2010 7,781,781'CMOS imager array with recessed dielectric'2010 7,772,028'CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom'2010 7,759,755'Anti-reflection structures for CMOS image sensors'2010 7,745,863'Flip FERAM cell and method to form same'2010 7,732,841'Pixel sensor cell for collecting electrons and holes'2010 7,732,845'Pixel sensor with reduced image lag'2010 7,723,178'Shallow and deep trench isolation structures in semiconductor integrated circuits'2010 7,719,118'Semiconductor chip scale package incorporating through-vias electrically connected to a substrate and other vias that are isolated from the substrate, and method of forming the package'2010 7,687,340'Protect diodes for hybrid-orientation substrate structures'2010 7,675,097'Silicide strapping in imager transfer gate device'2010 7,659,564'CMOS imager photodiode with enhanced capacitance'2010 7,659,497'On demand circuit function execution employing optical sensing'2010 7,655,495'Damascene copper wiring optical image sensor'2010 7,655,966'High efficiency CMOS image sensor pixel employing dynamic voltage supply'2010 7,633,042'Pixel sensor cell having a pinning layer surrounding collection well regions for collecting electrons and holes'2009 7,633,106'Light shield for CMOS imager'2009 7,622,364'Bond pad for wafer and package for CMOS imager'2009 7,620,931'Method of adding fabrication monitors to integrated circuit chips'2009 7,586,139'Photo-sensor and pixel array with backside illumination and method of forming the photo-sensor'2009 7,572,701'Recessed gate for a CMOS image sensor'2009 7,563,636'Method of forming a pixel sensor cell for collecting electrons and holes'2009 7,558,999'Learning based logic diagnosis'2009 7,524,694'Funneled light pipe for pixel sensors'2009 7,521,798'Stacked imager package'2009 7,494,748'Method for correction of defects in lithography masks'2009 7,492,048'CMOS sensors having charge pushing regions'2009 7,491,561'Pixel sensor having doped isolation structure sidewall'2009 7,491,992'Image sensor cells'2009 7,482,675'Probing pads in kerf area for wafer testing'2009 7,459,360'Method of forming pixel sensor cell having reduced pinning layer barrier potential'2008 7,446,007'Multi-layer spacer with inhibited recess/undercut and method for fabrication thereof'2008 7,439,561'Pixel sensor cell for collecting electrons and holes'2008 7,402,857'Flip FERAM cell and method to form same'2008 7,361,556'Method of fabricating semiconductor side wall fin'2008 7,361,581'High surface area aluminum bond pad for through-wafer connections to an electronic package'2008 7,361,989'Stacked imager package'2008 7,342,268'CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom'2008 7,323,278'Method of adding fabrication monitors to integrated circuit chips'2008 7,303,952'Method for fabricating doped polysilicon lines'2007 7,265,417'Method of fabricating semiconductor side wall fin'2007 7,240,322'Method of adding fabrication monitors to integrated circuit chips'2007 7,217,968'Recessed gate for an image sensor'2007 7,217,969'Flip FERAM cell and method to form same'2007 7,205,591'Pixel sensor cell having reduced pinning layer barrier potential and method thereof'2007 7,205,627'Image sensor cells'2007 7,194,706'Designing scan chains with specific parameter sensitivities to identify process defects'2007 7,193,289'Damascene copper wiring image sensor'2007 7,186,573'Flip FERAM cell and method to form same'2007 7,163,864'Method of fabricating semiconductor side wall fin'2007 7,141,836'Pixel sensor having doped isolation structure sidewall'2006 7,129,130'Out of the box vertical transistor for eDRAM on SOI'2006 7,112,845'Double gate trench transistor'2006 7,098,067'Masked sidewall implant for image sensor'2006 7,089,514'Defect diagnosis for semiconductor integrated circuits'2006 7,009,237'Out of the box vertical transistor for eDRAM on SOI'2006 6,960,744'Electrically tunable on-chip resistor'2005 6,858,889'Polysilicon capacitor having large capacitance and low resistance'2005 6,797,553'Method for making multiple threshold voltage FET using multiple work-function gate materials'2004 6,756,637'Method of controlling floating body effects in an asymmetrical SOI device'2004 6,670,255'Method of fabricating lateral diodes and bipolar transistors'2003 6,660,664'Structure and method for formation of a blocked silicide resistor'2003 6,660,596'Double planar gated SOI MOSFET structure'2003 6,653,710'Fuse structure with thermal and crack-stop protection'2003 6,590,259'Semiconductor device of an embedded DRAM on SOI substrate'2003 6,563,131'Method and structure of a dual/wrap-around gate field effect transistor'2003 6,555,859'Flip FERAM cell and method to form same'2003 6,483,156'Double planar gated SOI MOSFET structure'2002 6,472,258'Double gate trench transistor'2002 6,448,590'Multiple threshold voltage FET using multiple work-function gate materials'2002 6,445,194'Structure and method for electrical method of determining film conformality'2002 6,403,393'Device having integrated optical and copper conductors and method of fabricating same'2002 6,350,653'Embedded DRAM on silicon-on-insulator substrate'2002 6,333,202'Flip FERAM cell and method to form same'2001 6,326,260'Gate prespacers for high density, high performance DRAMs'2001 6,300,228'Multiple precipitation doping process'2001 6,261,895'Polysilicon capacitor having large capacitance and low resistance and process for forming the capacitor'2001 6,197,656'Method of forming planar isolation and substrate contacts in SIMOX-SOI.'2001 6,030,541'Process for defining a pattern using an anti-reflective coating and structure therefor'2000 6,015,745'Method for semiconductor fabrication'2000 4,453,848'Noise-reducing platen'1984 4,452,543'High speed printer with multiple paper paths'1984

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1984Based in S. Merrit Is., FL, US· patent location history

2000–2019Patents assigned to IBM (149)· patent assignee history

2000–2020Based in Jericho, VT, US· patent location history

2012–2016Patents assigned to ADKISSON JAMES W (29)· patent assignee history

2012–2015Patents assigned to GAMBINO JEFFREY P (14)· patent assignee history

2012–2015Patents assigned to JAFFE MARK D (14)· patent assignee history

2012Based in Essex Junction, VT, US· patent location history

2014Based in Jerico, VT, US· patent location history

2015–2020Patents assigned to GLOBALFOUNDRIES INC (18)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	149	2000–2019
ADKISSON JAMES Wself	29	2012–2016
GLOBALFOUNDRIES INC	18	2015–2020
GAMBINO JEFFREY P	14	2012–2015
JAFFE MARK D	14	2012–2015

Locations

Location	Patents	Span
Jericho, VT, US	160	2000–2020
S. Merrit Is., Florida, US	2	1984
Jerico, VT, US	1	2014
Essex Junction, VT, US	1	2012