Inventor

Shashi Kiran Chilappagari

Inventor

San Jose, CA, US

Overview

2013–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 39 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Mprimary

H03MCoding43%

G11CStatic stores24%

G06FElectric digital data processing22%

H04LTransmission of digital information, e.g. telegraphic communication10%

G11BInformation storage based on relative movement between record carrier and transducer2%

PatentTitleYear

10,790,857Systems and methods for using decoders of different complexity in a hybrid decoder architecture2020 10,587,288Systems and methods for iterative coding of product codes in nand FLASH controllers2020 10,411,735Systems and methods for an iterative decoding scheme2019 10,365,966Methods and systems for wordline based encoding and decoding in NAND flash2019 10,200,064Systems and method for bit-flipping decoders with partial-column processing, ordering and scheduling2019 10,153,786Iterative decoder with dynamically-variable performance2018 10,084,480Systems and methods for decoding cascade LDPC codes2018 10,038,456Decoders with look ahead logic2018 9,755,665'Systems and methods for an iterative decoding scheme'2017 9,614,548'Systems and methods for hybrid message passing and bit flipping decoding of LDPC codes'2017 9,577,675'System and method for encoding user data with low-density parity-check codes with flexible redundant parity check matrix structures'2017 9,564,931'Systems and methods for using decoders of different complexity in a hybrid decoder architecture'2017 9,548,764'Memory efficient decoders for low-density parity-check codes'2017 9,537,508'Systems and methods for decoding cascade LDPC codes'2017 9,467,170'NAND flash memory systems with efficient soft information interface'2016 9,437,320'Joint detecting and decoding system for nonvolatile semiconductor memory with reduced inter-cell interference'2016 9,385,753'Systems and methods for bit flipping decoding with reliability inputs'2016 9,379,738'Systems and methods for decoding using partial reliability information'2016 9,369,152'Systems and methods for decoding with late reliability information'2016 9,323,611'Systems and methods for multi-stage soft input decoding'2016 9,203,432'Symbol flipping decoders of non-binary low-density parity check (LDPC) codes'2015 9,183,942'Inter-cell interference cancellation'2015 9,153,323'Systems and methods for generating soft information in NAND flash'2015 9,153,336'Decoder parameter estimation using multiple memory reads'2015 9,152,558'Mapping different portions of data to different pages of multi-level non-volatile memory'2015 9,065,623'Mixed mapping for rate compatible trellis coded modulation'2015 9,009,574'Identification and mitigation of hard errors in memory systems'2015 8,984,378'Systems and methods for performing multi-state bit flipping in an LDPC decoder'2015 8,943,381'Systems and methods for performing bit flipping in an LDPC decoder'2015 8,913,437'Inter-cell interference cancellation'2014 8,885,415'Determining optimal reference voltages for progressive reads in flash memory systems'2014 8,875,000'Methods and systems systems for encoding and decoding in trellis coded modulation systems'2014 8,825,945'Mapping different portions of data to different pages of multi-level non-volatile memory'2014 8,694,868'Systems and methods for performing multi-state bit flipping in an LDPC decoder'2014 8,681,564'Systems and methods for generating soft information in NAND flash'2014 8,667,361'Systems and methods for performing bit flipping in an LDPC decoder'2014 8,576,625'Decoder parameter estimation using multiple memory reads'2013 8,531,888'Determining optimal reference voltages for progressive reads in flash memory systems'2013 8,458,556'Low complexity finite precision decoders and apparatus for LDPC codes'2013

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2013–2020Patents assigned to MARVELL INT LTD (22)· patent assignee history

2013–2016Patents assigned to MARVELL WORLD TRADE LTD (16)· patent assignee history

2013–2015Patents assigned to CHILAPPAGARI SHASHI KIRAN (10)· patent assignee history

2013–2015Patents assigned to YANG XUESHI (7)· patent assignee history

2013–2020Based in San Jose, CA, US· patent location history

2014–2015Patents assigned to BURD GREGORY (6)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MARVELL INT LTD	22	2013–2020
MARVELL WORLD TRADE LTD	16	2013–2016
CHILAPPAGARI SHASHI KIRANself	10	2013–2015
YANG XUESHI	7	2013–2015
BURD GREGORY	6	2014–2015

Locations

Location	Patents	Span
San Jose, California, US	39	2013–2020