Inventor
Ludovic Ecarnot
Inventor
Vaulnaveys le Haut, FR
Overview
Patents· 14 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1032%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1030%
H01LSemiconductor devices18%
H10DInorganic electric semiconductor devices9%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation5%
B28DWorking stone or stone-like materials2%
B81BMicrostructural devices or systems, e.g. micromechanical devices2%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems2%
PatentTitleYear
11,127,775Substrate for front side type imager and method of manufacturing such a substrate202111,127,624Method of manufacturing a semiconductor on insulator type structure, notably for a front side type imager202111,114,314Method for fabrication of a semiconductor structure including an interposer free from any through via202110,777,447Method for determining a suitable implanting energy in a donor substrate and process for fabricating a structure of semiconductor-on-insulator type202010,703,627Methods of fabricating semiconductor structures including cavities filled with a sacrificial material202010,163,682Methods of forming semiconductor structures20189,768,057'Method for transferring a layer from a single-crystal substrate'20178,962,492'Method to thin a silicon-on-insulator substrate'20158,389,412'Finishing method for a silicon on insulator substrate'20137,892,861'Method for fabricating a compound-material wafer'20117,883,628'Method of reducing the surface roughness of a semiconductor wafer'20117,749,910'Method of reducing the surface roughness of a semiconductor wafer'20107,138,344'Method for minimizing slip line faults on a semiconductor wafer surface'20066,962,858'Method for reducing free surface roughness of a semiconductor wafer'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2021Patents assigned to SOITEC SILICON ON INSULATOR (14)· patent assignee history
2005–2011Based in Varces, FR· patent location history
2006Based in Gieres, FR· patent location history
2011–2015Based in Vif, FR· patent location history
2013–2015Patents assigned to ECARNOT LUDOVIC (2)· patent assignee history
2013–2015Patents assigned to REYNAUD PATRICK (2)· patent assignee history
2013Patents assigned to KERDILES SEBASTIEN (1)· patent assignee history
2013Patents assigned to NEYRET ERIC (1)· patent assignee history
2017–2020Based in Vaulnaveys le Haut, FR· patent location history
2021Based in Grenoble, FR· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SOITEC SILICON ON INSULATOR | 14 | 2005–2021 |
| ECARNOT LUDOVICself | 2 | 2013–2015 |
| REYNAUD PATRICK | 2 | 2013–2015 |
| KERDILES SEBASTIEN | 1 | 2013 |
| NEYRET ERIC | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Vaulnaveys le Haut, FR | 4 | 2017–2020 |
| Vif, FR | 3 | 2011–2015 |
| Varces, FR | 3 | 2005–2011 |
| Grenoble, FR | 2 | 2021 |
| Gieres, FR | 1 | 2006 |