Inventor
AGOSTINO PIROVANO
Inventor
IT
Overview
Patents· 38 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores27%
H10NElectric solid-state devices not otherwise provided for23%
H10BElectronic memory devices22%
H01LSemiconductor devices15%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
H10DInorganic electric semiconductor devices4%
H10KOrganic electric solid-state devices1%
PatentTitleYear
12,462,870Reading a multi-level memory cell202512,349,371Vertical memory architecture202512,219,883Techniques for forming self-aligned memory structures202512,211,538Techniques to manufacture ferroelectric memory devices202512,176,042Operating a chalcogenide memory with vertical word and vertical word switching elements202412,131,793Triple modular redundancy for fault-tolerant in-memory computing202412,100,447Self-selecting memory array with horizontal access lines202412,082,513Memory cells with asymmetrical electrode interfaces202411,996,141Reading a multi-level memory cell202411,895,851Cross point array architecture for multiple decks202411,869,585Segregation-based memory202411,817,148Techniques for programming a memory cell202311,798,620Apparatuses including multi-level memory cells and methods of operation of same202311,769,551Multi-level self-selecting memory device202311,765,912Three dimensional memory arrays202311,763,886Techniques to access a self-selecting memory device202311,735,261Programming enhancement in self-selecting memory202311,721,394Polarity-written cell architectures for a memory device202311,696,454Three dimensional memory arrays202311,647,638Memory device with double protective liner202311,587,979Three dimensional memory array202311,574,957Three-dimensional memory array202311,545,625Tapered memory cell profiles202311,489,117Self-aligned memory decks in cross-point memory arrays202211,482,280Apparatuses including multi-level memory cells and methods of operation of same202211,475,951Material implication operations in memory202211,417,841Techniques for forming self-aligned memory structures202211,404,637Tapered cell profile and fabrication202211,404,479Memory including a selector switch on a variable resistance memory cell202211,404,117Self-selecting memory array with horizontal access lines202211,374,059Memory cells having resistors and formation of the same202211,302,748Arrays of memory cells and methods of forming an array of elevationally-outer-tier memory cells and elevationally-inner-tier memory cells202211,302,393Techniques for programming a memory cell202211,302,390Reading a multi-level memory cell202211,217,322Drift mitigation with embedded refresh202211,200,950Programming enhancement in self-selecting memory202111,164,627Polarity-written cell architectures for a memory device202111,152,065Techniques to access a self-selecting memory device2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2025Patents assigned to MICRON TECHNOLOGY INC (37)· patent assignee history
2021–2025Based in IT· patent location history
2023Patents assigned to INTEL CORP (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 37 | 2021–2025 |
| INTEL CORP | 1 | 2023 |
Locations
| Location | Patents | Span |
|---|---|---|
| IT | 38 | 2021–2025 |