Inventor

Tomasz Janczak

Inventor
Gdansk, PL

Overview

32→
Patents
2007–2021
Patent span
Physics
Primary field (CPC G)

Patents· 32 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Tprimary
G06TImage data processing or generation, in general50%
G06FElectric digital data processing30%
G09GArrangements or circuits for control of indicating devices using static means to present variable information9%
H04WWireless communication networks6%
G02BOptical elements, systems or apparatus4%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%
PatentTitleYear
11,120,766Graphics with adaptive temporal adjustments202111,087,542Replicating primitives across multiple viewports202111,062,506Tile-based immediate mode rendering with early hierarchical-z202111,049,214Deferred geometry rasterization technology202110,922,227Resource-specific flushes and invalidations of cache and memory fabric structures202110,896,657Graphics with adaptive temporal adjustments202110,853,995Physically based shading via fixed-functionality shader libraries202010,818,054Apparatus and method for asynchronous texel shading202010,803,549Systems and method for avoiding duplicative processing during generation of a procedural texture202010,783,603Graphics processor with tiled compute kernels202010,706,612Tile-based immediate mode rendering with early hierarchical-z202010,672,366Handling surface level coherency without reliance on fencing202010,521,271Hybrid low power homogenous grapics processing units201910,521,876Deferred geometry rasterization technology201910,430,189GPU register allocation mechanism201910,395,623Handling surface level coherency without reliance on fencing201910,347,039Physically based shading via fixed-functionality shader libraries201910,235,811Replicating primitives across multiple viewports201910,235,735Graphics processor with tiled compute kernels201910,089,230Resource-specific flushes and invalidations of cache and memory fabric structures20189,905,046'Mapping multi-rate shading to monolithic programs'20189,779,696'Serialized access to graphics resources'20179,606,919'Method and apparatus to facilitate shared pointers in a heterogeneous platform'20179,483,810'Reducing the number of IO requests to memory when executing a program that iteratively processes contiguous data'20169,449,360'Reducing the number of sequential operations in an application to be performed on a shared memory cell'20168,862,831'Method and apparatus to facilitate shared pointers in a heterogeneous platform'20148,566,537'Method and apparatus to facilitate shared pointers in a heterogeneous platform'20138,434,074'Register allocation with SIMD architecture using write masks'20137,856,465'Combined fast fourier transforms and matrix operations'20107,706,399'Polling in wireless networks'20107,366,153'Apparatus and method capable of providing quality of service channel access in a wireless network'20087,180,861'Strict priority distributed coordination function in wireless networks'2007

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2007–2021Patents assigned to INTEL CORP (32)· patent assignee history
2007–2021Based in Gdansk, PL· patent location history
2013–2016Patents assigned to JANCZAK TOMASZ (4)· patent assignee history
2013Patents assigned to ASHBAUGH BEN J (2)· patent assignee history
2013Patents assigned to ADL-TABATABAI ALI-REZA (1)· patent assignee history
2013Patents assigned to BARIK RAJKISHORE (1)· patent assignee history
2017Based in Folsom, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INTEL CORP322007–2021
JANCZAK TOMASZself42013–2016
ASHBAUGH BEN J22013
ADL-TABATABAI ALI-REZA12013
BARIK RAJKISHORE12013
Locations
LocationPatentsSpan
Gdansk, PL312007–2021
Folsom, California, US12017