Inventor

Oleg Gluschenkov

Inventor

Poughkeepsie, NY, US

Overview

2001–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 232 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices34%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1022%

H01LSemiconductor devices18%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%

H10BElectronic memory devices4%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%

G01RMeasuring electric variables2%

C23CCoating metallic material1%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%

H10NElectric solid-state devices not otherwise provided for1%

PatentTitleYear

11,114,606MRAM devices containing a harden gap fill dielectric material2021 11,107,968All-semiconductor Josephson junction device for qubit applications2021 11,088,280Transistor and method of forming same2021 11,075,280Self-aligned gate and junction for VTFET2021 11,069,854Laser anneal for MRAM encapsulation enhancement2021 11,069,809Soi FinFET fins with recessed fins and epitaxy in source drain region2021 11,031,246EUV pattern transfer with ion implantation and reduced impact of resist residue2021 11,022,887Tunable adhesion of EUV photoresist on oxide surface2021 11,004,984Low resistivity epitaxially formed contact region for nanosheet external resistance reduction2021 10,964,603Hybrid gate stack integration for stacked vertical transport field-effect transistors2021 10,957,781Uniform horizontal spacer2021 10,930,780Low parasitic capacitance and resistance finFET device2021 10,910,435Stackable symmetrical operation memory bit cell structure with bidirectional selectors2021 10,879,068Extreme ultraviolet lithography for high volume manufacture of a semiconductor device2020 10,833,150Fast recrystallization of hafnium or zirconium based oxides in insulator-metal structures2020 10,833,192Substantially defect free relaxed heterogeneous semiconductor fins on bulk substrates2020 10,832,973Stress modulation of nFET and pFET fin structures2020 10,804,270Contact formation through low-tempearature epitaxial deposition in semiconductor devices2020 10,804,106High temperature ultra-fast annealed soft mask for semiconductor devices2020 10,784,371Self aligned top extension formation for vertical transistors2020 10,777,464Low thermal budget top source and drain region formation for vertical transistors2020 10,777,468Stacked vertical field-effect transistors with sacrificial layer patterning2020 10,734,518Substantially defect free relaxed heterogeneous semiconductor fins on bulk substrates2020 10,692,768Vertical transport field-effect transistor architecture2020 10,692,868Contact formation through low-temperature epitaxial deposition in semiconductor devices2020 10,685,961Contact formation in semiconductor devices2020 10,665,512Stress modulation of nFET and pFET fin structures2020 10,658,180EUV pattern transfer with ion implantation and reduced impact of resist residue2020 10,651,089Low thermal budget top source and drain region formation for vertical transistors2020 10,651,308Self aligned top extension formation for vertical transistors2020 10,643,006Semiconductor chip including integrated security circuit2020 10,622,379Structure and method to form defect free high-mobility semiconductor fins on insulator2020 10,586,769Contact formation in semiconductor devices2020 10,551,742Tunable adhesion of EUV photoresist on oxide surface2020 10,553,439Multiple nanosecond laser pulse anneal processes and resultant semiconductor structure2020 10,529,828Method of forming vertical transistor having dual bottom spacers2020 10,510,617CMOS VFET contacts with trench solid and liquid phase epitaxy2019 10,388,789Reducing series resistance between source and/or drain regions and a channel region2019 10,381,442Low resistance source drain contact formation2019 10,374,088Low parasitic capacitance and resistance finFET device2019 10,361,306High acceptor level doping in silicon germanium2019 10,347,581Contact formation in semiconductor devices2019 10,319,855Reducing series resistance between source and/or drain regions and a channel region2019 10,319,722Contact formation in semiconductor devices2019 10,297,614Gate top spacer for FinFET2019 10,269,652Vertical transistor top epitaxy source/drain and contact structure2019 10,262,904Vertical transistor top epitaxy source/drain and contact structure2019 10,249,502Low resistance source drain contact formation with trench metastable alloys and laser annealing2019 10,236,360Method of forming vertical transistor having dual bottom spacers2019 10,211,207Low resistance source/drain contacts for complementary metal oxide semiconductor (CMOS) devices2019 10,170,620Substantially defect free relaxed heterogeneous semiconductor fins on bulk substrates2019 10,141,308Low resistance source/drain contacts for complementary metal oxide semiconductor (CMOS) devices2018 10,134,763Gate top spacer for finFET2018 10,115,824Forming a contact for a semiconductor device2018 10,109,722Etch-resistant spacer formation on gate structure2018 10,079,299Self aligned top extension formation for vertical transistors2018 10,068,920Silicon germanium fins on insulator formed by lateral recrystallization2018 10,032,883Silicon germanium heterojunction bipolar transistor structure and method2018 9,997,407Voidless contact metal structures2018 9,997,361Gate stack formed with interrupted deposition processes and laser annealing2018 9,997,610Gate stack formed with interrupted deposition processes and laser annealing2018 9,997,348Wafer stress control and topography compensation2018 9,985,114Fin field effect transistor structure and method to form defect free merged source and drain epitaxy for low external resistance2018 9,978,750Low resistance source/drain contacts for complementary metal oxide semiconductor (CMOS) devices2018 9,972,682Low resistance source drain contact formation2018 9,954,103Bottom spacer formation for vertical transistor2018 9,941,391Method of forming vertical transistor having dual bottom spacers2018 9,941,302Structure and method to form defect free high-mobility semiconductor fins on insulator2018 9,917,060'Forming a contact for a semiconductor device'2018 9,911,849'Transistor and method of forming same'2018 9,905,692'SOI FinFET fins with recessed fins and epitaxy in source drain region'2018 9,859,216'Voidless contact metal structures'2018 9,859,121'Multiple nanosecond laser pulse anneal processes and resultant semiconductor structure'2018 9,799,513'Localized elastic strain relaxed buffer'2017 9,799,736'High acceptor level doping in silicon germanium'2017 9,773,901'Bottom spacer formation for vertical transistor'2017 9,748,382'Self aligned top extension formation for vertical transistors'2017 9,748,359'Vertical transistor bottom spacer formation'2017 9,702,930'Semiconductor wafer probing system including pressure sensing and control unit'2017 9,679,810'Integrated circuit having improved electromigration performance and method of forming same'2017 9,620,416'Fin field effect transistor structure and method to form defect free merged source and drain epitaxy for low external resistance'2017 9,620,396'Laser anneal of buried metallic interconnects including through silicon vias'2017 9,613,870'Gate stack formed with interrupted deposition processes and laser annealing'2017 9,613,866'Gate stack formed with interrupted deposition processes and laser annealing'2017 9,570,298'Localized elastic strain relaxed buffer'2017 9,524,930'Configurable interposer'2016 9,455,185'Laser anneal of buried metallic interconnects including through silicon vias'2016 9,449,921'Voidless contact metal structures'2016 9,451,684'Dual pulse driven extreme ultraviolet (EUV) radiation source method'2016 9,450,069'Silicon germanium heterojunction bipolar transistor structure and method'2016 9,431,534'Asymmetric field effect transistor cap layer'2016 9,412,658'Constrained nanosecond laser anneal of metal interconnect structures'2016 9,378,952'Tall relaxed high percentage silicon germanium fins on insulator'2016 9,360,858'Alignment data based process control system'2016 9,354,252'Pressure sensing and control for semiconductor wafer probing'2016 9,349,661'Wafer thinning endpoint detection for TSV technology'2016 9,335,759'Optimization of a laser anneal beam path for maximizing chip yield'2016 9,301,381'Dual pulse driven extreme ultraviolet (EUV) radiation source utilizing a droplet comprising a metal core with dual concentric shells of buffer gas'2016 9,275,866'Gas cluster reactor for anisotropic film growth'2016 9,151,781'Yield enhancement for stacked chips through rotationally-connecting-interposer'2015 9,093,424'Dual silicide integration with laser annealing'2015 9,059,316'Structure and method for mobility enhanced MOSFETs with unalloyed silicide'2015 9,040,373'Silicon device on SI:C-OI and SGOI and method of manufacture'2015 8,963,567'Pressure sensing and control for semiconductor wafer probing'2015 8,759,152'Configurable interposer'2014 8,679,938'Shallow trench isolation for device including deep trench capacitors'2014 8,643,061'Structure of high-K metal gate semiconductor transistor'2014 8,642,434'Structure and method for mobility enhanced MOSFETS with unalloyed silicide'2014 8,633,071'Silicon device on Si: C-oi and Sgoi and method of manufacture'2014 8,557,652'Application of cluster beam implantation for fabricating threshold voltage adjusted FETs'2013 8,507,346'Method of forming a semiconductor device having a cut-way hole to expose a portion of a hardmask layer'2013 8,492,848'Application of cluster beam implantation for fabricating threshold voltage adjusted FETs'2013 8,455,322'Silicon germanium heterojunction bipolar transistor structure and method'2013 8,288,222'Application of cluster beam implantation for fabricating threshold voltage adjusted FETs'2012 8,237,278'Configurable interposer'2012 8,232,153'Silicon device on Si:C-OI and SGOI and method of manufacture'2012 8,227,316'Method for manufacturing double gate finFET with asymmetric halo'2012 8,217,423'Structure and method for mobility enhanced MOSFETs with unalloyed silicide'2012 8,159,247'Yield enhancement for stacked chips through rotationally-connecting-interposer'2012 8,119,472'Silicon device on Si:C SOI and SiGe and method of manufacture'2012 8,111,903'Inline low-damage automated failure analysis'2012 8,095,230'Method for optimizing the routing of wafers/lots based on yield'2012 8,067,805'Ultra shallow junction formation by epitaxial interface limited diffusion'2011 8,013,392'High mobility CMOS circuits'2011 7,968,944'Integrated circuit chip with FETs having mixed body thicknesses and method of manufacture thereof'2011 7,952,149'Anti-halo compensation'2011 7,932,136'Source/drain junction for high performance MOSFET formed by selective EPI process'2011 7,923,782'Hybrid SOI/bulk semiconductor transistors'2011 7,900,167'Silicon germanium heterojunction bipolar transistor structure and method'2011 7,847,358'High performance strained CMOS devices'2010 7,840,916'Structure for on-chip electromigration monitoring system'2010 7,824,989'Method for reducing overlap capacitance in field effect transistors'2010 7,816,237'Ultra shallow junction formation by epitaxial interface limited diffusion'2010 7,785,943'Method for forming a multi-gate device with high k dielectric for channel top surface'2010 7,786,025'Activating dopants using multiple consecutive millisecond-range anneals'2010 7,767,503'Hybrid SOI/bulk semiconductor transistors'2010 7,750,410'Structure and method to improve channel mobility by gate electrode stress modification'2010 7,750,371'Silicon germanium heterojunction bipolar transistor structure and method'2010 7,741,166'Oxidation method for altering a film structure'2010 7,732,288'Method for fabricating a semiconductor structure'2010 7,719,005'Structure and method for monitoring and characterizing pattern density dependence on thermal absorption in a semiconductor manufacturing process'2010 7,719,302'On-chip electromigration monitoring'2010 7,709,333'Method for reducing overlap capacitance in field effect transistors'2010 7,683,418'High-temperature stable gate structure with metallic electrode'2010 7,618,853'Field effect transistors with dielectric source drain halo regions and reduced miller capacitance'2009 7,615,435'Semiconductor device and method of manufacture'2009 7,605,447'Highly manufacturable SRAM cells in substrates with hybrid crystal orientation'2009 7,585,704'Method of producing highly strained PECVD silicon nitride thin films at low temperature'2009 7,569,848'Mobility enhanced CMOS devices'2009 7,560,328'Strained Si on multiple materials for bulk or SOI substrates'2009 7,521,760'Integrated circuit chip with FETs having mixed body thickness and method of manufacture thereof'2009 7,521,345'High-temperature stable gate structure with metallic electrode'2009 7,504,700'Method of forming an ultra-thin [[HfSiO]] metal silicate film for high performance CMOS applications and semiconductor structure formed in said method'2009 7,488,658'Stressed semiconductor device structures having granular semiconductor material'2009 7,452,761'Hybrid SOI-bulk semiconductor transistors'2008 7,446,004'Method for reducing overlap capacitance in field effect transistors'2008 7,402,870'Ultra shallow junction formation by epitaxial interface limited diffusion'2008 7,396,714'Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions'2008 7,394,273'On-chip electromigration monitoring system'2008 7,388,257'Multi-gate device with high k dielectric for channel top surface'2008 7,355,245'Structure for reducing overlap capacitance in field effect transistors'2008 7,354,806'Semiconductor device structure with active regions having different surface directions and methods'2008 7,342,266'Field effect transistors with dielectric source drain halo regions and reduced miller capacitance'2008 7,312,134'Dual stressed SOI substrates'2007 7,291,528'Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions'2007 7,285,826'High mobility CMOS circuits'2007 7,285,480'Integrated circuit chip with FETs having mixed body thicknesses and method of manufacture thereof'2007 7,282,403'Temperature stable metal nitride gate electrode'2007 7,279,413'High-temperature stable gate structure with metallic electrode'2007 7,271,049'Method of forming self-aligned low-k gate cap'2007 7,262,087'Dual stressed SOI substrates'2007 7,253,482'Structure for reducing overlap capacitance in field effect transistors'2007 7,247,547'Method of fabricating a field effect transistor having improved junctions'2007 7,247,534'Silicon device on Si:C-OI and SGOI and method of manufacture'2007 7,232,774'Polycrystalline silicon layer with nano-grain structure and method of manufacture'2007 7,230,296'Self-aligned low-k gate cap'2007 7,223,994'Strained Si on multiple materials for bulk or SOI substrates'2007 7,205,206'Method of fabricating mobility enhanced CMOS devices'2007 7,205,207'High performance strained CMOS devices'2007 7,202,516'CMOS transistor structure including film having reduced stress by exposure to atomic oxygen'2007 7,198,995'Strained finFETs and method of manufacture'2007 7,176,116'High performance FET with laterally thin extension'2007 7,170,126'Structure of vertical strained silicon devices'2007 7,160,771'Forming gate oxides having multiple thicknesses'2007 7,144,767'NFETs using gate induced stress modulation'2006 7,138,685'Vertical MOSFET SRAM cell'2006 7,122,849'Stressed semiconductor device structures having granular semiconductor material'2006 7,119,403'High performance strained CMOS devices'2006 7,084,024'Gate electrode forming methods using conductive hard mask'2006 7,030,012'Method for manufacturing tungsten/polysilicon word line structure in vertical DRAM'2006 7,026,247'Nanocircuit and self-correcting etching method for fabricating same'2006 7,023,041'Trench capacitor vertical structure'2006 7,023,064'Temperature stable metal nitride gate electrode'2006 7,015,082'High mobility CMOS circuits'2006 7,002,209'MOSFET structure with high mechanical stress in the channel'2006 6,989,322'Method of forming ultra-thin silicidation-stop extensions in mosfet devices'2006 6,982,196'Oxidation method for altering a film structure and CMOS transistor structure formed therewith'2006 6,977,194'Structure and method to improve channel mobility by gate electrode stress modification'2005 6,975,133'Logic circuits having linear and cellular gate transistors'2005 6,974,991'DRAM cell with buried collar and self-aligned buried strap'2005 6,960,514'Pitcher-shaped active area for field effect transistor and method of forming same'2005 6,933,577'High performance FET with laterally thin extension'2005 6,930,060'Method for forming a uniform distribution of nitrogen in silicon oxynitride gate dielectric'2005 6,911,384'Gate structure with independently tailored vertical doping profile'2005 6,908,806'Gate metal recess for oxidation protection and parasitic capacitance reduction'2005 6,890,833'Trench isolation employing a doped oxide trench fill'2005 6,891,192'Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions'2005 6,878,582'Low-GIDL MOSFET structure and method for fabrication'2005 6,873,010'High performance logic and high density embedded dram with borderless contact and antispacer'2005 6,841,826'Low-GIDL MOSFET structure and method for fabrication'2005 6,838,334'Method of fabricating a buried collar'2005 6,806,534'Damascene method for improved MOS transistor'2004 6,797,582'Vertical thermal nitride mask (anti-collar) and processing thereof'2004 6,764,883'Amorphous and polycrystalline silicon nanolaminate'2004 6,746,933'Pitcher-shaped active area for field effect transistor and method of forming same'2004 6,727,142'Orientation independent oxidation of nitrided silicon'2004 6,723,611'Vertical hard mask'2004 6,720,630'Structure and method for MOSFET with metallic gate electrode'2004 6,709,926'High performance logic and high density embedded dram with borderless contact and antispacer'2004 6,686,637'Gate structure with independently tailored vertical doping profile'2004 6,667,197'Method for differential oxidation rate reduction for n-type and p-type materials'2003 6,656,798'Gate processing method with reduced gate oxide corner and edge thinning'2003 6,576,565'RTCVD process and reactor for improved conformality and step-coverage'2003 6,566,210'Method of improving gate activation by employing atomic oxygen enhanced oxidation'2003 6,555,166'Method for reducing the microloading effect in a chemical vapor deposition reactor'2003 6,544,874'Method for forming junction on insulator (JOI) structure'2003 6,514,843'Method of enhanced oxidation of MOS transistor gate corners'2003 6,509,221'Method for forming high performance CMOS devices with elevated sidewall spacers'2003 6,451,662'Method of forming low-leakage on-chip capacitor'2002 6,444,516'Semi-insulating diffusion barrier for low-resistivity gate conductors'2002 6,358,867'Orientation independent oxidation of silicon'2002 6,261,972'Dual gate oxide process for uniform oxide thickness'2001

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2001–2021Patents assigned to IBM (219)· patent assignee history

2001–2013Based in Hopewell Junction, NY, US· patent location history

2002–2021Based in Poughkeepsie, NY, US· patent location history

2002–2007Based in Wappingers Falls, NY, US· patent location history

2010–2021Based in Tannersville, NY, US· patent location history

2012–2016Patents assigned to GLUSCHENKOV OLEG (19)· patent assignee history

2012–2015Patents assigned to CHIDAMBARRAO DURESETI (5)· patent assignee history

2012–2015Patents assigned to SONG YUNSHENG (5)· patent assignee history

2016–2019Patents assigned to GLOBALFOUNDRIES INC (12)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	219	2001–2021
GLUSCHENKOV OLEGself	19	2012–2016
GLOBALFOUNDRIES INC	12	2016–2019
CHIDAMBARRAO DURESETI	5	2012–2015
SONG YUNSHENG	5	2012–2015

Locations

Location	Patents	Span
Poughkeepsie, New York, US	102	2002–2021
Tannersville, New York, US	98	2010–2021
Wappingers Falls, New York, US	26	2002–2007
Hopewell Junction, New York, US	6	2001–2013