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Inventor

Alejandro Lenero Beracoechea

Inventor
Phoenix, AZ, US

Overview

4→
Patents
2008–2018
Patent span
Physics
Primary field (CPC G)

Patents· 4 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing50%
H04JMultiplex communication50%
PatentTitleYear
9,864,711'Automatic downstream to upstream mode switching at a universal serial bus physical layer'20188,539,131'Root hub virtual transaction translator'20137,656,891'Method and apparatus enabling concurrent processing of contiguously and virtually concatenated payloads'20107,460,545'Enhanced SDRAM bandwidth usage and memory management for TDM traffic'2008

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2008–2018Patents assigned to INTEL CORP (4)· patent assignee history
2008–2010Based in Dublin, CA, US· patent location history
2013–2018Patents assigned to BERACOECHEA ALEJANDRO LENERO (2)· patent assignee history
2013–2018Patents assigned to CHANG NAI-CHIH (2)· patent assignee history
2013–2018Patents assigned to WANG JENNIFER C (2)· patent assignee history
2013–2018Based in Phoenix, AZ, US· patent location history
2018Patents assigned to MCGOWAN STEVEN B (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INTEL CORP42008–2018
BERACOECHEA ALEJANDRO LENEROself22013–2018
CHANG NAI-CHIH22013–2018
WANG JENNIFER C22013–2018
MCGOWAN STEVEN B12018
Locations
LocationPatentsSpan
Phoenix, AZ, US22013–2018
Dublin, California, US22008–2010