Inventor
Robert Feurle
Inventor
Neubiberg, DE
Overview
Patents· 32 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores37%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1020%
H10BElectronic memory devices10%
H10DInorganic electric semiconductor devices6%
G01RMeasuring electric variables4%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices4%
G05FSystems for regulating electric or magnetic variables4%
H03KPulse technique4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
H02JElectric power networks2%
PatentTitleYear
7,078,133'Photolithographic mask'20066,922,764'Memory, processor system and method for performing write operations on a memory region'20056,894,379'Sharing of multiple-access signal line in a printed circuit board'20056,816,432'Integrated semiconductor circuit having transistors that are switched with different frequencies'20046,781,220'Printed circuit board for semiconductor memory device'20046,768,693'Integrated dynamic memory with control circuit for controlling a refresh mode of memory cells, and method for driving the memory'20046,751,145'Volatile semiconductor memory and mobile device'20046,728,143'Integrated memory'20046,707,705'Integrated dynamic memory device and method for operating an integrated dynamic memory'20046,700,831'Integrated memory having a plurality of memory cell arrays and method for operating the integrated memory'20046,646,908'Integrated memory chip with a dynamic memory'20036,643,211'Integrated memory having a plurality of memory cell arrays'20036,639,825'Data memory'20036,628,553'Data output interface, in particular for semiconductor memories'20036,615,289'Semiconductor chip configuration and method of controlling a semiconductor chip'20036,614,706'Voltage regulating circuit, in particular for semiconductor memories'20036,528,392'Dicing configuration for separating a semiconductor component from a semiconductor wafer'20036,492,729'Configuration and method for connecting conductor tracks'20026,480,039'Input buffer of an integrated semiconductor circuit'20026,456,522'Integrated memory having memory cells and buffer capacitors'20026,441,469'Semiconductor memory configuration with dummy components on continuous diffusion regions'20026,433,617'Configuration for reducing the number of measuring pads on a semiconductor chip'20026,426,899'Integrated memory with a buffer circuit'20026,317,374'Method for operating a current sense amplifier'20016,317,378'Buffer circuit'20016,310,399'Semiconductor memory configuration with a bit-line twist'20016,302,729'Integrated circuit with electrical connection points that can be severed by the action of energy'20016,294,841'Integrated semiconductor circuit having dummy structures'20016,281,586'Integrated semiconductor circuit configuration having stabilized conductor tracks'20016,240,005'Sense amplifier configuration with fused diffusion regions and a distributed driver system'20016,236,612'Integrated semiconductor memory configuration with self-buffering of supply voltages'20016,205,044'Decoder connection configuration for memory chips with long bit lines'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2006Patents assigned to INFINEON TECHNOLOGIES AG (30)· patent assignee history
2001Patents assigned to SIEMENS AG (2)· patent assignee history
2001–2006Based in Neubiberg, DE· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INFINEON TECHNOLOGIES AG | 30 | 2001–2006 |
| SIEMENS AG | 2 | 2001 |
Locations
| Location | Patents | Span |
|---|---|---|
| Neubiberg, DE | 32 | 2001–2006 |