Inventor
Jun-Wei Chen
Inventor
Saratoga, CA, US
Overview
Patents· 44 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices33%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests14%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%
H01LSemiconductor devices6%
C08FMacromolecular compounds obtained by reactions only involving carbon-to-carbon unsaturated bonds4%
B32BLayered products, i.e. products built-up of strata of flat or non-flat, e.g. cellular or honeycomb, form2%
C08GMacromolecular compounds obtained otherwise than by reactions only involving unsaturated carbon-to-carbon bonds2%
C08JWorking-up2%
C08KUse of inorganic or non-macromolecular organic substances as compounding ingredients2%
PatentTitleYear
10,844,180Structure of phosphorous-containing functionalized poly(arylene ether), composition containing the same, and copper clad laminate202010,563,019Structure of phosphorous-containing functionalized poly(arylene ether) and compositions prepared therefrom202010,344,110Functionalized polydicyclopentadiene polymer201910,184,053Pigment-type ultraviolet light curable coating for window film and preparation method therefor20199,985,019Semiconductor structure with high-voltage and low-voltage CMOS devices and method for manufacturing the same20189,966,096Self-assembled nanoparticles with polymeric and/or oligomeric ligands20189,666,699'Semiconductor device having field plate disposed on isolation feature and method for forming the same'20179,553,091'Semiconductor structure and method for manufacturing the same'20179,548,354'Semiconductor devices and methods for fabricating the same'20179,530,900'Schottky diode and method for manufacturing the same'20169,525,045'Semiconductor devices and methods for forming the same'20168,659,086'ESD protection for bipolar-CMOS-DMOS integrated circuit devices'20148,338,217'Method of fabricating a solar cell'20128,097,522'Modular methods of forming isolation structures for integrated circuits'20127,994,578'ESD protection for bipolar-CMOS-DMOS integrated circuit devices'20117,956,437'Isolation structures for integrated circuits'20117,812,393'High-voltage extended drain MOSFET'20107,738,224'ESD protection for bipolar-CMOS-DMOS integrated circuit devices'20107,719,054'High-voltage lateral DMOS device'20107,626,243'ESD protection for bipolar-CMOS-DMOS integrated circuit devices'20097,216,971'Eyeglass with lens fastening arrangement'20076,271,278'Hydrogel composites and superporous hydrogel composites having fast swelling, high mechanical strength, and superabsorbent properties'20016,018,033'Hydrophilic, hydrophobic, and thermoreversible saccharide gels and forms, and methods for producing same'20005,751,054'Zener diodes on the same wafer with BiCDMOS structures'19985,648,281'Method for forming an isolation structure and a bipolar transistor on a semiconductor substrate'19975,643,820'Method for fabricating an MOS capacitor using zener diode region'19975,618,743'MOS transistor having adjusted threshold voltage formed along with other transistors'19975,583,061'PMOS transistors with different breakdown voltages formed in the same substrate'19965,559,044'BiCDMOS process technology'19965,547,880'Method for forming a zener diode region and an isolation region'19965,541,125'Method for forming a lateral MOS transistor having lightly doped drain formed along with other transistors in the same substrate'19965,541,123'Method for forming a bipolar transistor having selected breakdown voltage'19965,521,409'Structure of power mosfets, including termination structures'19965,451,533'Bidirectional blocking lateral MOSFET with improved on-resistance'19955,439,842'Low temperature oxide layer over field implant mask'19955,429,964'Low on-resistance power MOS technology'19955,426,328'BICDMOS structures'19955,422,508'BiCDMOS structure'19955,420,451'Bidirectional blocking lateral MOSFET with improved on-resistance'19955,416,039'Method of making BiCDMOS structures'19955,404,040'Structure and fabrication of power MOSFETs, including termination structures'19955,374,569'Method for forming a BiCDMOS'19945,328,866'Low temperature oxide layer over field implant mask'19945,304,831'Low on-resistance power MOS technology'1994Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994–1998Patents assigned to SILICONIX INC (21)· patent assignee history
1994–2014Based in Saratoga, CA, US· patent location history
2000–2001Based in Hatfield, PA, US· patent location history
2007–2014Patents assigned to CHEN JUN-WEI (4)· patent assignee history
2009–2014Patents assigned to ADVANCED ANALOGIC TECH INC (8)· patent assignee history
2012–2014Patents assigned to CHAN WAI TIEN (2)· patent assignee history
2016–2018Patents assigned to VANGUARD INT SEMICONDUCT CORP (6)· patent assignee history
2016–2018Based in Hsinchu, TW· patent location history
2019Based in Victoria, CA· patent location history
2020Based in Jiangsu Province, CN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SILICONIX INC | 21 | 1994–1998 |
| ADVANCED ANALOGIC TECH INC | 8 | 2009–2014 |
| VANGUARD INT SEMICONDUCT CORP | 6 | 2016–2018 |
| CHEN JUN-WEIself | 4 | 2007–2014 |
| CHAN WAI TIEN | 2 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Saratoga, California, US | 28 | 1994–2014 |
| Hsinchu, TW | 6 | 2016–2018 |
| Jiangsu Province, CN | 2 | 2020 |
| Hatfield, Pennsylvania, US | 2 | 2000–2001 |
| Victoria, CA | 1 | 2019 |