Inventor
CHIEH-JEN KU
Inventor
US
Overview
Patents· 31 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices28%
H10BElectronic memory devices24%
H01LSemiconductor devices23%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1015%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
G11CStatic stores2%
H10NElectric solid-state devices not otherwise provided for2%
PatentTitleYear
12,599,032Bilayer memory stacking with lines shared between bottom and top memory layers202612,513,970Integrated circuits with tungsten interconnect liners202512,471,318Low defect, high mobility thin film transistors with in-situ doped metal oxide channel material202512,446,208Multilevel wordline assembly for embedded DRAM202512,426,247Capacitor connections in dielectric layers202512,376,342Passivation layers for thin film transistors202512,310,001Decoupling capacitors and methods of fabrication202512,238,913Two transistor memory cell using stacked thin-film transistors202512,176,284Through plate interconnect for a vertical MIM capacitor202412,148,734Transistors, memory cells, and arrangements thereof202412,150,297Thin film transistors having a backside channel contact for high density memory202412,080,781Fabrication of thin film fin transistor structure202412,080,643Integrated circuit structures having differentiated interconnect lines in a same dielectric layer202411,991,873Capacitor separations in dielectric layers202411,973,105Embedded precision resistor for non-planar semiconductor device architectures202411,955,560Passivation layers for thin film transistors and methods of fabrication202411,929,415Thin film transistors with offset source and drain structures and process for forming such202411,908,911Thin film transistors with raised source and drain contacts and process for forming such202411,832,438Capacitor connections in dielectric layers202311,810,980Channel formation for three dimensional transistors202311,784,088Isolation gap filling process for embedded dram using spacer material202311,758,711Thin-film transistor embedded dynamic random-access memory with shallow bitline202311,683,929Method for making memory cells based on thin-film transistors202311,652,047Intermediate separation layers at the back-end-of-line202311,610,894Capacitor separations in dielectric layers202311,563,107Method of contact patterning of thin film transistors for embedded DRAM using a multi-layer hardmask202311,462,541Memory cells based on vertical thin-film transistors202211,450,669Stacked thin-film transistor based embedded dynamic random-access memory202211,404,536Thin-film transistor structures with gas spacer202211,393,927Memory cells based on thin-film transistors202211,329,047Thin-film transistor embedded dynamic random-access memory with shallow bitline2022Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2022–2026Patents assigned to INTEL CORP (31)· patent assignee history
2022Patents assigned to INTEL COROPRATION (1)· patent assignee history
2022–2026Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 31 | 2022–2026 |
| INTEL COROPRATION | 1 | 2022 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 31 | 2022–2026 |