Inventor
Ram S. Viswanath
Inventor
Phoenix, AZ, US
Overview
Patents· 27 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1034%
H01LSemiconductor devices20%
H05KPrinted circuits16%
H01RElectrically-conductive connections10%
F28DHeat-exchange apparatus, not provided for in another subclass, in which the heat-exchange media do not come into direct contact3%
G01RMeasuring electric variables3%
H01BCables3%
Y02PClimate change mitigation technologies in the production or processing of goods3%
F28FDetails of heat-exchange and heat-transfer apparatus, of general application2%
G06FElectric digital data processing2%
PatentTitleYear
10,784,204Rlink--die to die channel interconnect configurations to improve signaling202010,643,945Pitch translation architecture for semiconductor package including embedded interconnect bridge202010,424,561Integrated circuit structures with recessed conductive contacts for package on package201910,187,996Printed circuit board with a recess to accommodate discrete components in a package20199,865,568'Integrated circuit structures with recessed conductive contacts for package on package'20189,832,876CPU package substrates with removable memory mechanical interfaces20179,674,954'Chip package connector assembly'20179,640,887'Low profile zero/low insertion force package top side flex cable connector architecture'20179,603,247'Electronic package with narrow-factor via including finish layer'20179,461,014'Methods of forming ultra thin package structures including low temperature solder and structures formed therby'20169,391,013'3D integrated circuit package with window interposer'20169,324,678'Low profile zero/low insertion force package top side flex cable connector architecture'20169,265,170'Integrated circuit connectors'20169,129,958'3D integrated circuit package with window interposer'20159,064,971'Methods of forming ultra thin package structures including low temperature solder and structures formed therby'20158,513,792'Package-on-package interconnect stiffener'20136,979,208'Laminated socket contacts'20056,888,722'Thermal design for minimizing interface in a multi-site thermal contact condition'20056,854,979'Laminated socket contacts'20056,672,880'Laminated socket contacts'20046,575,766'Laminated socket contacts'20036,493,223'Computer utilizing refrigeration for cooling'20026,189,601'Heat sink with a heat pipe for spreading of heat'20016,072,322'Thermally enhanced test socket'20006,049,217'Thermally enhanced test contactor'20006,019,166'Pickup chuck with an integral heatsink'20005,944,093'Pickup chuck with an integral heat pipe'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2020Patents assigned to INTEL CORP (27)· patent assignee history
1999–2020Based in Phoenix, AZ, US· patent location history
2013–2016Patents assigned to VISWANATH RAM S (3)· patent assignee history
2013–2016Patents assigned to GANESAN SANKA (2)· patent assignee history
2013Patents assigned to ARANA LEONEL R (1)· patent assignee history
2015Patents assigned to AGRAHARAM SAIRAM (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 27 | 1999–2020 |
| VISWANATH RAM Sself | 3 | 2013–2016 |
| GANESAN SANKA | 2 | 2013–2016 |
| AGRAHARAM SAIRAM | 1 | 2015 |
| ARANA LEONEL R | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Phoenix, AZ, US | 27 | 1999–2020 |