Inventor
Krishnashree Achuthan
Inventor
San Ramon, CA, US
Overview
Patents· 33 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1029%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1025%
H10DInorganic electric semiconductor devices11%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests11%
H10BElectronic memory devices5%
C09GPolishing compositions4%
G06FElectric digital data processing4%
B24BMachines, devices, or processes for grinding or polishing3%
Y10TTechnical subjects covered by former us classification3%
G01JMeasurement of intensity, velocity, spectral content, polarisation, phase or pulse characteristics of infrared, visible or ultraviolet light1%
PatentTitleYear
10,295,404Solar monitoring system for measuring solar radiation intensity201910,057,382Intelligent "IoT gateway"201810,055,607Security layer and methods for protecting tenant data in a cloud-mediated computing network20189,710,664'Security layer and methods for protecting tenant data in a cloud-mediated computing network'20177,449,413'Method for effectively removing polysilicon nodule defects'20087,358,191'Method for decreasing sheet resistivity variations of an interconnect metal layer'20087,307,002'Non-critical complementary masking method for poly-1 definition in flash memory device fabrication'20077,294,573'Method for controlling poly 1 thickness and uniformity in a memory array fabrication process'20077,125,776'Multi-step chemical mechanical polishing of a gate area in a FinFET'20067,077,728'Method for reducing edge array erosion in a high-density array'20067,052,969'Method for semiconductor wafer planarization by isolation material growth'20066,989,563'Flash memory cell with UV protective layer'20066,982,464'Dual silicon layer for chemical mechanical polishing planarization'20066,933,219'Tightly spaced gate formation through damascene process'20056,855,607'Multi-step chemical mechanical polishing of a gate area in a FinFET'20056,812,076'Dual silicon layer for chemical mechanical polishing planarization'20046,770,523'Method for semiconductor wafer planarization by CMP stop layer formation'20046,756,643'Dual silicon layer for chemical mechanical polishing planarization'20046,649,511'Method of manufacturing a seed layer with annealed region for integrated circuit interconnects'20036,613,646'Methods for reduced trench isolation step height'20036,610,577'Self-aligned polysilicon polish'20036,607,925'Hard mask removal process including isolation dielectric refill'20036,605,517'Method for minimizing nitride residue on a silicon wafer'20036,569,747'Methods for trench isolation with reduced step height'20036,559,546'Tin palladium activation with maximized nuclei density and uniformity on barrier material in interconnect structure'20036,498,397'Seed layer with annealed region for integrated circuit interconnects'20026,498,093'Formation without vacuum break of sacrificial layer that dissolves in acidic activation solution within interconnect'20026,472,310'Tin palladium activation with maximized nuclei density and uniformity on barrier material in interconnect structure'20026,462,409'Semiconductor wafer polishing apparatus'20026,426,297'Differential pressure chemical-mechanical polishing in integrated circuit interconnects'20026,423,433'Method of forming Cu-Ca-O thin films on Cu surfaces in a chemical solution and semiconductor device thereby'20026,413,869'Dielectric protected chemical-mechanical polishing in integrated circuit interconnects'20026,291,348'Method of forming Cu-Ca-O thin films on Cu surfaces in a chemical solution and semiconductor device thereby formed'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2008Patents assigned to ADVANCED MICRO DEVICES INC (28)· patent assignee history
2001–2008Based in San Ramon, CA, US· patent location history
2007–2008Patents assigned to SPANSION LLC (3)· patent assignee history
2017–2019Patents assigned to AMRITA VISHWA VIDYAPEETHAM (4)· patent assignee history
2017–2019Patents assigned to ACHUTHAN KRISHNASHREE (2)· patent assignee history
2017–2018Based in Kerala, IN· patent location history
2018Patents assigned to Amrita Vistiwa Vidyapeetham (1)· patent assignee history
2019Based in Kollam, IN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED MICRO DEVICES INC | 28 | 2001–2008 |
| AMRITA VISHWA VIDYAPEETHAM | 4 | 2017–2019 |
| SPANSION LLC | 3 | 2007–2008 |
| ACHUTHAN KRISHNASHREEself | 2 | 2017–2019 |
| Amrita Vistiwa Vidyapeetham | 1 | 2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Ramon, California, US | 29 | 2001–2008 |
| Kerala, IN | 3 | 2017–2018 |
| Kollam, IN | 1 | 2019 |