Inventor
Joseph Zbiciak
Inventor
San Jose, CA, US
Overview
Patents· 49 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing64%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use14%
H03MCoding6%
H03HImpedance networks, e.g. resonant circuits4%
H04NPictorial communication, e.g. television4%
G06KGraphical data reading1%
G06TImage data processing or generation, in general1%
G11CStatic stores1%
H03KPulse technique1%
H04JMultiplex communication1%
PatentTitleYear
11,119,776Cache management operations using streaming engine202111,106,591Streaming engine with separately selectable element and group duplication202111,106,463System and method for addressing data in memory202111,101,825Butterfly network on load data return202111,086,778Multicore shared cache operation engine202111,080,047Register file structures combining vector and scalar data with global and local accesses202111,036,648Highly integrated scalable, flexible DSP megamodule architecture202110,963,247Vector floating-point classification202110,963,254Mechanism to queue multiple streams to run on streaming engine202110,949,206Transposing a matrix using a streaming engine202110,942,741Storage organization for transposing a matrix using a streaming engine202110,936,315Tracking streaming engine vector predicates to control processor execution202110,936,317Streaming address generation202110,901,913Two address translations from a single table look-aside buffer read202110,810,131Streaming engine with multi dimensional circular addressing selectable at each dimension202010,678,545Data processing apparatus having streaming engine with read and read/advance operand coding202010,592,243Streaming engine with cache-like stream data storage and lifetime tracking202010,572,255Stream engine with element promotion and decimation modes202010,459,843Streaming engine with separately selectable element and group duplication201910,387,354Superimposing butterfly network controls for pattern combinations201910,339,057Streaming engine with flexible streaming engine template supporting differing number of nested loops with corresponding loop counts and loop offsets201910,318,433Streaming engine with multi dimensional circular addressing selectable at each dimension201910,303,611Streaming engine with compressed encoding for loop circular buffer sizes201910,140,239Superimposing butterfly network controls for pattern combinations201810,073,696Streaming engine with cache-like stream data storage and lifetime tracking20189,965,278Streaming engine with compressed encoding for loop circular buffer sizes2018RE046193'Distributed power control for controlling power consumption based on detected activity of logic blocks'20169,009,414'Prefetch address hit prediction to reduce memory access latency'20158,977,819'Prefetch stream filter with FIFO allocation and stream direction prediction'20158,806,110'Flexible memory protection and translation unit'20148,788,759'Double-buffered data storage to reduce prefetch generation stalls'20148,707,013'On-demand predicate registers'20148,683,114'Device security features supporting a distributed shared memory system'20148,682,639'Dedicated memory window for emulation address'20148,683,115'Programmable mapping of external requestors to privilege classes for access protection'20148,627,032'Memory protection unit with support for distributed permission checks'20148,601,221'Speculation-aware memory controller arbiter'20137,890,566'Microprocessor with rounding dot product instruction'20117,576,758'Using super-pixels for efficient in-place rotation of images'20097,315,261'Method for converting data from pixel format to bitplane format'20086,892,380'Method for software pipelining of irregular conditional control loops'20056,819,684'Deterministic bit insertion into serial communications'20046,801,985'Data bus using synchronous fixed latency loop including read address and data busses and write address and data busses'20046,757,819'Microprocessor with instructions for shifting data responsive to a signed count value'20046,754,893'Method for collapsing the prolog and epilog of software pipelined loops'20046,691,240'System and method of implementing variabe length delay instructions, which prevents overlapping lifetime information or values in efficient way'20046,574,724'Microprocessor with non-aligned scaled and unscaled addressing'20036,560,288'Method and system for variable length decoding'20036,453,405'Microprocessor with non-aligned circular addressing'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2021Patents assigned to TEXAS INSTRUMENTS INC (49)· patent assignee history
2002–2011Based in North Richland Hills, TX, US· patent location history
2008–2015Based in Arlington, TX, US· patent location history
2013–2015Patents assigned to ZBICIAK JOSEPH R M (8)· patent assignee history
2013–2015Patents assigned to ANDERSON TIMOTHY D (4)· patent assignee history
2013–2015Patents assigned to CHIRCA KAI (2)· patent assignee history
2014–2015Patents assigned to PIERSON MATTHEW D (3)· patent assignee history
2016–2020Based in Farmers Branch, TX, US· patent location history
2018–2021Based in San Jose, CA, US· patent location history
2021Based in Alviso, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TEXAS INSTRUMENTS INC | 49 | 2002–2021 |
| ZBICIAK JOSEPH R Mself | 8 | 2013–2015 |
| ANDERSON TIMOTHY D | 4 | 2013–2015 |
| PIERSON MATTHEW D | 3 | 2014–2015 |
| CHIRCA KAI | 2 | 2013–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 17 | 2018–2021 |
| Arlington, Texas, US | 12 | 2008–2015 |
| North Richland Hills, Texas, US | 9 | 2002–2011 |
| Farmers Branch, Texas, US | 6 | 2016–2020 |
| Alviso, California, US | 4 | 2021 |